[tb] Add support to trace retired TCDM operations

Bender.yml

@@ -28,6 +28,7 @@ sources:
   - hardware/src/mempool_cc.sv
   - hardware/src/snitch_addr_demux.sv
   - hardware/src/tcdm_adapter.sv
+  - hardware/src/tcdm_adapter_xqueue.sv
   - hardware/src/tcdm_shim.sv
   - hardware/src/tcdm_wide_narrow_mux.sv
   - hardware/src/address_scrambler.sv

CHANGELOG.md

@@ -9,6 +9,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ### Added
 - Add a DMA
+- Add support to hardrware-accelerated queues for CGRA (RV32A extension)
+- Add systolic implementation of matmul and 2d convolution exploiting hardware-accelerated queues
+- Add ability to Trace the operations retired by the TCDM adapters  
 
 ### Fixed
 - Measure the `wfi` stalls and stalls caused by `opc` properly
@@ -34,7 +37,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Add the `terapool` configuration
 - Add read-only caches to the hierarchical AXI interconnect
 - Add a `memcpy` benchmark
-- Add a systolic configuration including runtime support and a matmul application
+- Add a systolic configuration for software-emulated CGRA including runtime support and a systolic matmul
 - Add `axpy` kernel
 - Add Spyglass linting scripts
 - Add an OpenMP runtime and example applications

CONTRIBUTORS.md

@@ -11,4 +11,5 @@ Thanks to all.
 * Marc Gantenbein
 * Marco Bertuletti
 * Sergio Mazzola
+* Vaibhav Krishna
 * Yichao Zhang

config/README.md

@@ -10,6 +10,7 @@ flavors of MemPool. We currently support three flavors:
 - `terapool`: 1024 cores, organized into 128 tiles with eight cores each
 - `mempool`: 256 cores, organized into 64 tiles with four cores each (default)
 - `minpool`: 16 cores, organized into 4 tiles with four cores each
+- `systolic`: same as `mempool` but the cores form a CGRA
 
 Use the `config` variable to define which configuration to take. For example,
 to run a simulation with the `minpool` configuration, you would run

config/config.mk

@@ -56,6 +56,9 @@ dmas_per_group ?= 4
 ##  Xqueues configuration  ##
 #############################
 
+# Hardware queues for systolic (atomic ISA extension in TCDM adapter)
+xqueue ?= 0
+
 # XQueue extension's queue size in each memory bank (in words)
 xqueue_size ?= 0
 

config/mempool.mk

@@ -17,6 +17,9 @@ num_groups ?= 4
 # Number of cores per MemPool tile
 num_cores_per_tile ?= 4
 
+# L1 scratchpad banking factor
+banking_factor ?= 4
+
 # Radix for hierarchical AXI interconnect
 axi_hier_radix ?= 20
 

config/minpool.mk

@@ -17,6 +17,9 @@ num_groups ?= 4
 # Number of cores per MemPool tile
 num_cores_per_tile ?= 4
 
+# L1 scratchpad banking factor
+banking_factor ?= 4
+
 # Number of DMA backends in each group
 dmas_per_group ?= 1
 

config/systolic.mk

@@ -15,8 +15,11 @@ num_groups ?= 4
 # Number of cores per MemPool tile
 num_cores_per_tile ?= 4
 
+# L1 scratchpad banking factor
+banking_factor ?= 4
+
 # Radix for hierarchical AXI interconnect
-axi_hier_radix ?= 16
+axi_hier_radix ?= 20
 
 # Number of AXI masters per group
 axi_masters_per_group ?= 1
@@ -29,6 +32,10 @@ seq_mem_size ?= 2048
 ##  Xqueues configuration  ##
 #############################
 
-# Xqueue extension's queue size (in queue entries)
-# in each memory bank (assume banking factor of 4)
+# Hardware queues for systolic (atomic ISA extension in TCDM adapter)
+xqueue ?= 1
+
+# Systolic queues size (assume banking factor of 4) for:
+# - software queues emulation (size measured in queue entries)
+# - hardware xqueue's queue in each memory bank (size measured in words)
 xqueue_size ?= 4

config/terapool.mk

@@ -17,6 +17,9 @@ num_groups ?= 8
 # Number of cores per Terapool tile
 num_cores_per_tile ?= 8
 
+# L1 scratchpad banking factor
+banking_factor ?= 4
+
 # Radix for hierarchical AXI interconnect
 axi_hier_radix ?= 8
 

hardware/Makefile

@@ -47,6 +47,7 @@ verilator_top   ?= mempool_tb_verilator
 python          ?= python3
 # Enable tracing
 snitch_trace    ?= 0
+bank_trace		  ?= 0
 
 # Check if the specified QuestaSim version exists
 ifeq (, $(shell which $(questa_cmd)))
@@ -87,15 +88,19 @@ endif
 vlog_args += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233
 vlog_args += -work $(library)
 # Defines
-vlog_defs += -DNUM_CORES=$(num_cores) -DNUM_CORES_PER_TILE=$(num_cores_per_tile) -DNUM_GROUPS=$(num_groups)
+vlog_defs += -DNUM_CORES=$(num_cores) -DNUM_CORES_PER_TILE=$(num_cores_per_tile) -DNUM_GROUPS=$(num_groups) -DBANKING_FACTOR=$(banking_factor)
 vlog_defs += -DL2_BASE=$(l2_base) -DL2_SIZE=$(l2_size) -DL2_BANKS=$(l2_banks)
 vlog_defs += -DBOOT_ADDR=$(boot_addr) -DXPULPIMG=$(xpulpimg)
-vlog_defs += -DSNITCH_TRACE=$(snitch_trace)
+vlog_defs += -DSNITCH_TRACE=$(snitch_trace) -DBANK_TRACE=$(bank_trace)
 vlog_defs += -DAXI_DATA_WIDTH=$(axi_data_width)
 vlog_defs += -DRO_LINE_WIDTH=$(ro_line_width)
 vlog_defs += -DDMAS_PER_GROUP=$(dmas_per_group)
 vlog_defs += -DAXI_HIER_RADIX=$(axi_hier_radix) -DAXI_MASTERS_PER_GROUP=$(axi_masters_per_group)
-vlog_defs += -DSEQ_MEM_SIZE=$(seq_mem_size) -DXQUEUE_SIZE=$(xqueue_size)
+vlog_defs += -DSEQ_MEM_SIZE=$(seq_mem_size) -DXQUEUE=$(xqueue) -DXQUEUE_SIZE=$(xqueue_size)
+
+ifeq ($(xqueue),1)
+	vlog_defs+= -DXQUEUE_TCDM_ADAPTER 
+endif
 
 # Traffic generation enabled
 ifdef tg

hardware/deps/snitch/src/riscv_instr.sv

@@ -935,6 +935,8 @@ package riscv_instr;
   localparam logic [31:0] PV_PACK_H          = 32'b1101001??????????000?????1010111;
   localparam logic [31:0] PV_PACKHI_B        = 32'b1101100??????????001?????1010111;
   localparam logic [31:0] PV_PACKLO_B        = 32'b1110000??????????001?????1010111;
+  localparam logic [31:0] Q_PUSH             = 32'b00111????????????010?????0101111;
+  localparam logic [31:0] Q_POP              = 32'b00110??00000?????010?????0101111;
   /* CSR Addresses */
   localparam logic [11:0] CSR_FFLAGS = 12'h1;
   localparam logic [11:0] CSR_FRM = 12'h2;

hardware/deps/snitch/src/snitch.sv

@@ -18,7 +18,8 @@ module snitch
   parameter logic [31:0] MTVEC     = BootAddr, // Exception Base Address (see privileged spec 3.1.7)
   parameter bit          RVE       = 0,   // Reduced-register Extension
   parameter bit          RVM       = 1,   // Enable IntegerMmultiplication & Division Extension
-  parameter int    RegNrWritePorts = 2    // Implement one or two write ports into the register file
+  parameter int    RegNrWritePorts = 2,   // Implement one or two write ports into the register file
+  parameter bit          Xqueue    = 0
 ) (
   input  logic          clk_i,
   input  logic          rst_i,
@@ -152,7 +153,10 @@ module snitch
     AMOMin  = 4'h8,
     AMOMinu = 4'h9,
     AMOLR   = 4'hA,
-    AMOSC   = 4'hB
+    AMOSC   = 4'hB,
+    // TODO(smazzola): parametrize
+    QPush   = 4'hC, // Only used when Xqueue is enabled
+    QPop    = 4'hD  // Only used when Xqueue is enabled
   } ls_amo;
 
   logic [31:0] ld_result;
@@ -1324,6 +1328,41 @@ module snitch
       end
 /* end of Xpulpimg extension */
 
+/* Xqueues extension */
+      // TODO(khovg): Add define to include instr
+      riscv_instr::Q_PUSH: begin
+        if (Xqueue) begin
+          alu_op = BypassA;
+          write_rd = 1'b0;
+          uses_rd = 1'b1;
+          is_load = 1'b1;
+          is_signed = 1'b1;
+          ls_size = Word;
+          ls_amo = QPush;
+          opa_select = Reg;
+          opb_select = Reg;
+        end else begin
+          illegal_inst = 1'b1;
+        end
+      end
+      // TODO(khovg): Two source registers are unnnecessary
+      riscv_instr::Q_POP: begin
+        if (Xqueue) begin
+          alu_op = BypassA;
+          write_rd = 1'b0;
+          uses_rd = 1'b1;
+          is_load = 1'b1;
+          is_signed = 1'b1;
+          ls_size = Word;
+          ls_amo = QPop;
+          opa_select = Reg;
+          opb_select = Reg;
+        end else begin
+          illegal_inst = 1'b1;
+        end
+      end
+/* end of Xqueues extension */
+
       // TODO(zarubaf): Illegal Instructions
       default: begin
         illegal_inst = 1'b1;

hardware/src/mempool_cc.sv

@@ -57,10 +57,11 @@ module mempool_cc
 
   // Snitch Integer Core
   snitch #(
-    .BootAddr ( BootAddr ),
-    .MTVEC    ( MTVEC    ),
-    .RVE      ( RVE      ),
-    .RVM      ( RVM      )
+    .BootAddr ( BootAddr            ),
+    .MTVEC    ( MTVEC               ),
+    .RVE      ( RVE                 ),
+    .RVM      ( RVM                 ),
+    .Xqueue   ( mempool_pkg::Xqueue )
   ) i_snitch (
     .clk_i                                   ,
     .rst_i                                   ,

hardware/src/mempool_pkg.sv

@@ -35,7 +35,7 @@ package mempool_pkg;
   localparam integer unsigned DataWidth        = 32;
   localparam integer unsigned BeWidth          = DataWidth / 8;
   localparam integer unsigned ByteOffset       = $clog2(BeWidth);
-  localparam integer unsigned BankingFactor    = 4;
+  localparam integer unsigned BankingFactor    = `ifdef BANKING_FACTOR `BANKING_FACTOR `else 0 `endif;
   localparam bit              LrScEnable       = 1'b1;
   localparam integer unsigned TCDMSizePerBank  = 1024; // [B]
   localparam integer unsigned NumBanks         = NumCores * BankingFactor;
@@ -258,6 +258,9 @@ package mempool_pkg;
    *  QUEUE PARAMETERS  *
    **********************/
 
+  // Size of queues in words (must be a power of two)
+  localparam bit Xqueue = `ifdef XQUEUE `XQUEUE `else 1'b0 `endif;
+
   // Size of xqueues in words (must be a power of two)
   localparam int unsigned XQueueSize = `ifdef XQUEUE_SIZE `XQUEUE_SIZE `else 0 `endif;
 

hardware/src/mempool_tile.sv

@@ -381,34 +381,65 @@ module mempool_tile
     assign bank_resp_payload[b].rdata.amo     = '0; // Don't care
     assign bank_resp_wide[b]                  = meta_out.wide;
 
-    tcdm_adapter #(
-      .AddrWidth  (TCDMAddrMemWidth),
-      .DataWidth  (DataWidth       ),
-      .metadata_t (bank_metadata_t ),
-      .LrScEnable (LrScEnable      ),
-      .RegisterAmo(1'b0            )
-    ) i_tcdm_adapter (
-      .clk_i       (clk_i                                                                       ),
-      .rst_ni      (rst_ni                                                                      ),
-      .in_valid_i  (bank_req_valid[b]                                                           ),
-      .in_ready_o  (bank_req_ready[b]                                                           ),
-      .in_address_i(bank_req_payload[b].tgt_addr[idx_width(NumBanksPerTile) +: TCDMAddrMemWidth]),
-      .in_amo_i    (bank_req_payload[b].wdata.amo                                               ),
-      .in_write_i  (bank_req_payload[b].wen                                                     ),
-      .in_wdata_i  (bank_req_payload[b].wdata.data                                              ),
-      .in_meta_i   (meta_in                                                                     ),
-      .in_be_i     (bank_req_payload[b].be                                                      ),
-      .in_valid_o  (bank_resp_valid[b]                                                          ),
-      .in_ready_i  (bank_resp_ready[b]                                                          ),
-      .in_rdata_o  (bank_resp_payload[b].rdata.data                                             ),
-      .in_meta_o   (meta_out                                                                    ),
-      .out_req_o   (req_valid                                                                   ),
-      .out_add_o   (req_addr                                                                    ),
-      .out_write_o (req_write                                                                   ),
-      .out_wdata_o (req_wdata                                                                   ),
-      .out_be_o    (req_be                                                                      ),
-      .out_rdata_i (resp_rdata                                                                  )
-    );
+    if (Xqueue) begin: gen_tcdm_adapter_xqueue
+      tcdm_adapter_xqueue #(
+        .AddrWidth  (TCDMAddrMemWidth),
+        .DataWidth  (DataWidth       ),
+        .XQueueSize (XQueueSize      ),
+        .metadata_t (bank_metadata_t ),
+        .RegisterAmo(1'b0            )
+      ) i_tcdm_adapter (
+        .clk_i       (clk_i                                                                       ),
+        .rst_ni      (rst_ni                                                                      ),
+        .in_valid_i  (bank_req_valid[b]                                                           ),
+        .in_ready_o  (bank_req_ready[b]                                                           ),
+        .in_address_i(bank_req_payload[b].tgt_addr[idx_width(NumBanksPerTile) +: TCDMAddrMemWidth]),
+        .in_amo_i    (bank_req_payload[b].wdata.amo                                               ),
+        .in_write_i  (bank_req_payload[b].wen                                                     ),
+        .in_wdata_i  (bank_req_payload[b].wdata.data                                              ),
+        .in_meta_i   (meta_in                                                                     ),
+        .in_be_i     (bank_req_payload[b].be                                                      ),
+        .in_valid_o  (bank_resp_valid[b]                                                          ),
+        .in_ready_i  (bank_resp_ready[b]                                                          ),
+        .in_rdata_o  (bank_resp_payload[b].rdata.data                                             ),
+        .in_meta_o   (meta_out                                                                    ),
+        .out_req_o   (req_valid                                                                   ),
+        .out_add_o   (req_addr                                                                    ),
+        .out_write_o (req_write                                                                   ),
+        .out_wdata_o (req_wdata                                                                   ),
+        .out_be_o    (req_be                                                                      ),
+        .out_rdata_i (resp_rdata                                                                  )
+      );
+    end else begin: gen_tcdm_adapter
+      tcdm_adapter #(
+        .AddrWidth  (TCDMAddrMemWidth),
+        .DataWidth  (DataWidth       ),
+        .metadata_t (bank_metadata_t ),
+        .LrScEnable (LrScEnable      ),
+        .RegisterAmo(1'b0            )
+      ) i_tcdm_adapter (
+        .clk_i       (clk_i                                                                       ),
+        .rst_ni      (rst_ni                                                                      ),
+        .in_valid_i  (bank_req_valid[b]                                                           ),
+        .in_ready_o  (bank_req_ready[b]                                                           ),
+        .in_address_i(bank_req_payload[b].tgt_addr[idx_width(NumBanksPerTile) +: TCDMAddrMemWidth]),
+        .in_amo_i    (bank_req_payload[b].wdata.amo                                               ),
+        .in_write_i  (bank_req_payload[b].wen                                                     ),
+        .in_wdata_i  (bank_req_payload[b].wdata.data                                              ),
+        .in_meta_i   (meta_in                                                                     ),
+        .in_be_i     (bank_req_payload[b].be                                                      ),
+        .in_valid_o  (bank_resp_valid[b]                                                          ),
+        .in_ready_i  (bank_resp_ready[b]                                                          ),
+        .in_rdata_o  (bank_resp_payload[b].rdata.data                                             ),
+        .in_meta_o   (meta_out                                                                    ),
+        .out_req_o   (req_valid                                                                   ),
+        .out_add_o   (req_addr                                                                    ),
+        .out_write_o (req_write                                                                   ),
+        .out_wdata_o (req_wdata                                                                   ),
+        .out_be_o    (req_be                                                                      ),
+        .out_rdata_i (resp_rdata                                                                  )
+      );
+    end
 
     // Bank
     tc_sram #(