Maoyuan/masking

hw/ip/snitch/src/riscv_instr.sv

@@ -1338,4 +1338,5 @@ package riscv_instr;
   localparam logic [11:0] CSR_MHPMCOUNTER29H = 12'hb9d;
   localparam logic [11:0] CSR_MHPMCOUNTER30H = 12'hb9e;
   localparam logic [11:0] CSR_MHPMCOUNTER31H = 12'hb9f;
+
 endpackage

hw/ip/snitch/src/snitch.sv

@@ -2335,6 +2335,16 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
       riscv_instr::VREDMINU_VS,
       riscv_instr::VREDMAX_VS,
       riscv_instr::VREDMAXU_VS,
+      // CMY: add VMANDNOT VMAND VMOR VMXOR VMORNOT VMNAND VMNOR VMXNOR, 8 masking instructions
+      riscv_instr::VMANDN_MM,
+      riscv_instr::VMAND_MM,
+      riscv_instr::VMOR_MM,
+      riscv_instr::VMXOR_MM,
+      riscv_instr::VMORN_MM,
+      riscv_instr::VMNAND_MM,
+      riscv_instr::VMNOR_MM,
+      riscv_instr::VMXNOR_MM,
+      //----------------------------------------------------------
       riscv_instr::VMSEQ_VV,
       riscv_instr::VMSEQ_VI,
       riscv_instr::VMSNE_VV,

hw/ip/spatz/src/spatz.sv

@@ -289,7 +289,7 @@ module spatz import spatz_pkg::*; import rvv_pkg::*; import fpnew_pkg::*; #(
     .vfu_rsp_o        (vfu_rsp                                                 ),
     // VRF
     .vrf_waddr_o      (vrf_waddr[VFU_VD_WD]                                    ),
-    .vrf_wdata_o      (vrf_wdata[VFU_VD_WD]                                    ),
+    .vrf_wdata_o      (vrf_wdata[VFU_VD_WD]                                    ), // N_FU*ELEN bits
     .vrf_we_o         (sb_we[VFU_VD_WD]                                        ),
     .vrf_wbe_o        (vrf_wbe[VFU_VD_WD]                                      ),
     .vrf_wvalid_i     (vrf_wvalid[VFU_VD_WD]                                   ),

hw/ip/spatz/src/spatz_controller.sv

@@ -199,7 +199,7 @@ module spatz_controller
   logic       req_buffer_ready, req_buffer_valid, req_buffer_pop;
 
   // One element wide instruction buffer
-  fall_through_register #(
+  fall_through_register #( // a fifo.
     .T(spatz_req_t)
   ) i_req_buffer (
     .clk_i     (clk_i                ),
@@ -339,6 +339,12 @@ module spatz_controller
         scoreboard_d[spatz_req.id].deps[write_table_d[spatz_req.vd].id] |= write_table_d[spatz_req.vd].valid;
         read_table_d[spatz_req.vd] = {spatz_req.id, 1'b1};
       end
+      // CMY: tackling v0 RAW hazard-------------------------------------------------------
+      if (!spatz_req.op_arith.vm) begin
+        scoreboard_d[spatz_req.id].deps[write_table_d[0].id] |= write_table_d[0].valid;
+        read_table_d[0] = {spatz_req.id, 1'b1};
+      end
+      //--------------------------------------------------------------------------------------
 
       // WAW and WAR hazards
       if (spatz_req.use_vd) begin
@@ -454,7 +460,7 @@ module spatz_controller
     running_insn_d = running_insn_q;
 
     // New instruction!
-    if (spatz_req_valid && spatz_req.ex_unit != CON)
+    if (spatz_req_valid && spatz_req.ex_unit != CON) // declare a new instruction
       running_insn_d[next_insn_id] = 1'b1;
 
     // Finished a instruction

hw/ip/spatz/src/spatz_decoder.sv

@@ -274,6 +274,16 @@ module spatz_decoder
         riscv_instr::VREDMINU_VS,
         riscv_instr::VREDMAX_VS,
         riscv_instr::VREDMAXU_VS,
+// CMY: add VMANDNOT VMAND VMOR VMXOR VMORNOT VMNAND VMNOR VMXNOR, 8 masking instructions
+        riscv_instr::VMANDN_MM,
+        riscv_instr::VMAND_MM,
+        riscv_instr::VMOR_MM,
+        riscv_instr::VMXOR_MM,
+        riscv_instr::VMORN_MM,
+        riscv_instr::VMNAND_MM,
+        riscv_instr::VMNOR_MM,
+        riscv_instr::VMXNOR_MM,
+//-------------------------------------------------------------
         riscv_instr::VMSEQ_VV,
         riscv_instr::VMSEQ_VX,
         riscv_instr::VMSEQ_VI,
@@ -348,7 +358,7 @@ module spatz_decoder
           automatic vreg_t arith_s1       = decoder_req_i.instr[19:15];
           automatic vreg_t arith_s2       = decoder_req_i.instr[24:20];
           automatic vreg_t arith_d        = decoder_req_i.instr[11:7];
-          automatic logic arith_vm        = decoder_req_i.instr[25];
+          automatic logic arith_vm        = decoder_req_i.instr[25]; //Vector Arithmetic Masking Enable bit
 
           spatz_req.op_arith.vm = arith_vm;
           spatz_req.op_sld.vm   = arith_vm;
@@ -827,6 +837,39 @@ module spatz_decoder
               end
             end
 
+       // CMY: Mask operations
+            riscv_instr::VMANDN_MM: begin
+              spatz_req.op = VMANDNOT;
+            end
+
+            riscv_instr::VMAND_MM: begin
+              spatz_req.op = VMAND;
+            end
+
+            riscv_instr::VMOR_MM: begin
+              spatz_req.op = VMOR;
+            end
+
+            riscv_instr::VMXOR_MM: begin
+              spatz_req.op = VMXOR;
+            end
+
+          riscv_instr::VMORN_MM: begin
+              spatz_req.op = VMORNOT;
+            end
+
+          riscv_instr::VMNAND_MM: begin
+              spatz_req.op = VMNAND;
+            end
+
+          riscv_instr::VMNOR_MM: begin
+              spatz_req.op = VMNOR;
+            end
+
+          riscv_instr::VMXNOR_MM: begin
+              spatz_req.op = VMXNOR;
+            end
+
             default: illegal_instr = 1'b1;
           endcase // Arithmetic Instruction Type
         end

hw/ip/spatz/src/spatz_ipu.sv

@@ -478,6 +478,7 @@ module spatz_ipu import spatz_pkg::*; import rvv_pkg::vew_e; #(
     ///////////////
 
     // Collect results from the SIMD lanes
+    // each lane is responsible for calculating one element.
     always_comb begin : collector
       unique case (sew)
         rvv_pkg::EW_8 : begin

hw/ip/spatz/src/spatz_pkg.sv.tpl

@@ -108,6 +108,10 @@ package spatz_pkg;
   typedef logic [$clog2(NrVRFWords)-1:0] vrf_addr_t;
   typedef logic [N_FU*ELENB-1:0] vrf_be_t;
   typedef logic [N_FU*ELEN-1:0] vrf_data_t;
+  // ELEN = 64
+  // The VRF is centralized and serves all functional units.
+  // Each VRF port is 64F-bit wide. F denotes the number of FPUs.
+  // the FU here doesn't refer to Functioan Units. N_FU=max{N_IPU,N_FPU}
 
   // Instruction ID
   typedef logic [$clog2(NrParallelInstructions)-1:0] spatz_id_t;

hw/ip/spatz/src/spatz_simd_lane.sv

@@ -220,9 +220,14 @@ module spatz_simd_lane import spatz_pkg::*; import rvv_pkg::vew_e; #(
         VSUB, VRSUB, VNMSAC, VNMSUB, VSBC: simd_result = subtractor_result[Width-1:0];
         VMIN, VMINU                      : simd_result = $signed({op_s1_i[Width-1] & is_signed_i, op_s1_i}) <= $signed({op_s2_i[Width-1] & is_signed_i, op_s2_i}) ? op_s1_i : op_s2_i;
         VMAX, VMAXU                      : simd_result = $signed({op_s1_i[Width-1] & is_signed_i, op_s1_i}) > $signed({op_s2_i[Width-1] & is_signed_i, op_s2_i}) ? op_s1_i : op_s2_i;
-        VAND                             : simd_result = op_s1_i & op_s2_i;
-        VOR                              : simd_result = op_s1_i | op_s2_i;
-        VXOR                             : simd_result = op_s1_i ^ op_s2_i;
+        VAND, VMAND                      : simd_result = op_s1_i & op_s2_i; // CMY: add masking support
+        VOR , VMOR                       : simd_result = op_s1_i | op_s2_i; // like above
+        VXOR, VMXOR                      : simd_result = op_s1_i ^ op_s2_i; // like above
+        VMANDNOT                         : simd_result = ~op_s1_i & op_s2_i; // like above
+        VMORNOT                          : simd_result = ~op_s1_i | op_s2_i; // like above
+        VMNAND                           : simd_result = ~(op_s1_i & op_s2_i); // like above
+        VMNOR                            : simd_result = ~(op_s1_i | op_s2_i); // like above
+        VMXNOR                           : simd_result = ~(op_s1_i ^ op_s2_i); // like above
         VSLL                             : simd_result = shift_operand << shift_amount;
         VSRL                             : simd_result = shift_operand >> shift_amount;
         VSRA                             : simd_result = $signed(shift_operand) >>> shift_amount;