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Why is == on a newtype wrapping bits resolved to eq_anything instead of eq_bits?

Status: Open.

#1682 In rems-project/sail;

· rez5427 opened on Jun 5, 2026

Add backends generator for compiler/simulator plugin description

Status: Open.

#1677 In rems-project/sail;

· rjiejie opened on May 26, 2026

Stack overflow building RISC-V model (OCaml 4.14.2)

Status: Open.

#1674 In rems-project/sail;

· arichardson opened on May 9, 2026

More efficient implementation of read_mem (lib/rts.c)

Status: Open.

#1671 In rems-project/sail;

· xokdvium opened on May 2, 2026

Lean termination proofs with matching on tuples

Status: Open.

#1659 In rems-project/sail;

· bacam opened on Apr 9, 2026

Segfault with weird register initialisation code

Status: Open.

#1653 In rems-project/sail;

· Timmmm opened on Apr 6, 2026

Strange flow typing failure

Status: Open.

#1652 In rems-project/sail;

· Timmmm opened on Apr 3, 2026

C backend uses sail_int for integers above 2^63

Status: Open.

#1651 In rems-project/sail;

· Timmmm opened on Apr 2, 2026

Compile scattered functions into separate functions and call them directly when parameter is known at compile time

Status: Open.

#1647 In rems-project/sail;

· Timmmm opened on Mar 29, 2026

Type inferred for unsigned(0x10) is less precise than 16

enhancementNew feature or requestNew feature or request

Status: Open.

#1643 In rems-project/sail;

· Timmmm opened on Mar 17, 2026

Support model snapshot - save & restore state

Status: Open.

#1642 In rems-project/sail;

· Timmmm opened on Mar 16, 2026

SV backend: bvashr applies signed' to shift amount instead of data operand

bugSomething isn't workingSomething isn't working

SystemVerilogIssues with Sail to SystemVerilog translationIssues with Sail to SystemVerilog translation

Status: Open.

#1632 In rems-project/sail;

· cwfletcher opened on Feb 25, 2026