The RISC-V Advanced Interrupt Architecture (AIA) builds upon the interrupt-handling functionality of the basic RISC-V ISA to add support mainly for the following:
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Message-signaled interrupts (MSIs) from devices.
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Direct control of device interrupts (as MSIs) by a guest operating system running in virtual supervisor mode (VS mode), reducing the reliance on regular hypervisor intervention.
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Additional standard local interrupts for RISC-V harts.
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Intermixing of priorities of local interrupts and device (external) interrupts.
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Conditional delegation of local interrupts to lower privilege levels, including to virtual machines.
A pre-built PDF is usually available under Releases: https://github.com/riscv/riscv-aia/releases
The files in this repository are licensed under the Creative Commons Attribution 4.0 International License (CC-BY 4.0). The full license text is available at https://creativecommons.org/licenses/by/4.0/.
