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Commit ebd2150

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linsinan1995linsinan1995
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remove minw, maxw and bpick
1 parent e78ce2b commit ebd2150

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11 files changed

+3
-50
lines changed

11 files changed

+3
-50
lines changed

‎gas/config/tc-riscv.c‎

Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1160,9 +1160,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
11601160
char field_name[RVP_MAX_KEYWORD_LEN];
11611161
if (parse_rvp_field (&p, field_name))
11621162
{
1163-
if (strcmp (field_name, "nds_rc") == 0)
1164-
USE_BITS (OP_MASK_RC, OP_SH_RC);
1165-
else if (strcmp (field_name, "nds_rdp") == 0)
1163+
if (strcmp (field_name, "nds_rdp") == 0)
11661164
USE_BITS (OP_MASK_RD, OP_SH_RD);
11671165
else if (strcmp (field_name, "nds_rsp") == 0)
11681166
USE_BITS (OP_MASK_RD, OP_SH_RS1);
@@ -2496,14 +2494,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
24962494
args++;
24972495
if (parse_rvp_field (&args, field_name))
24982496
{
2499-
if (strcmp (field_name, "nds_rc") == 0
2500-
&& reg_lookup (&s, RCLASS_GPR, &regno))
2501-
{
2502-
INSERT_OPERAND (RC, *ip, regno);
2503-
args--;
2504-
continue;
2505-
}
2506-
else if (strcmp (field_name, "nds_rdp") == 0
2497+
if (strcmp (field_name, "nds_rdp") == 0
25072498
&& reg_lookup (&s, RCLASS_GPR, &regno))
25082499
{
25092500
if (xlen == 32 && (regno % 2) != 0)

‎gas/testsuite/gas/riscv/insn-dsp-zbpbo.d‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,10 @@ Disassembly of section .text:
1111
[ ]+.*:[ ]+.*[ ]+clz[ ]+a1,a2
1212
[ ]+.*:[ ]+.*[ ]+clz[ ]+a1,a2
1313
[ ]+.*:[ ]+.*[ ]+cmix[ ]+a1,a2,a3,a4
14-
[ ]+.*:[ ]+.*[ ]+cmix[ ]+a0,a2,a1,a3
1514
[ ]+.*:[ ]+.*[ ]+fsr[ ]+a1,a2,a3,a4
1615
[ ]+.*:[ ]+.*[ ]+fsri[ ]+a1,a2,a3,0x5
1716
[ ]+.*:[ ]+.*[ ]+max[ ]+a1,a2,a3
1817
[ ]+.*:[ ]+.*[ ]+min[ ]+a1,a2,a3
19-
[ ]+.*:[ ]+.*[ ]+max[ ]+a1,a2,a3
20-
[ ]+.*:[ ]+.*[ ]+min[ ]+a1,a2,a3
2118
[ ]+.*:[ ]+.*[ ]+pack[ ]+a1,a2,a3
2219
[ ]+.*:[ ]+.*[ ]+packu[ ]+a1,a2,a3
2320
[ ]+.*:[ ]+.*[ ]+pack[ ]+a1,a2,a3

‎gas/testsuite/gas/riscv/insn-dsp-zbpbo.s‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,10 @@ dsp:
22
clz a1,a2
33
clz32 a1,a2
44
cmix a1,a2,a3,a4
5-
bpick a0,a1,a3,a2
65
fsr a1,a2,a3,a4
76
fsri a1,a2,a3,5
87
max a1,a2,a3
98
min a1,a2,a3
10-
maxw a1,a2,a3
11-
minw a1,a2,a3
129
pack a1,a2,a3
1310
packu a1,a2,a3
1411
pktt16 a1,a2,a3

‎gas/testsuite/gas/riscv/insn-dsp.d‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -239,11 +239,8 @@ Disassembly of section .text:
239239
[ ]+.*:[ ]+.*[ ]+bitrevi[ ]+a1,a2,5
240240
[ ]+.*:[ ]+.*[ ]+wext[ ]+a1,a2,a3
241241
[ ]+.*:[ ]+.*[ ]+wexti[ ]+a1,a2,5
242-
[ ]+.*:[ ]+.*[ ]+bpick[ ]+a1,a2,a3,a4
243242
[ ]+.*:[ ]+.*[ ]+insb[ ]+a1,a2,2
244243
[ ]+.*:[ ]+.*[ ]+maddr32[ ]+a2,a4,a6
245-
[ ]+.*:[ ]+.*[ ]+maxw[ ]+a2,a4,a6
246-
[ ]+.*:[ ]+.*[ ]+minw[ ]+a2,a4,a6
247244
[ ]+.*:[ ]+.*[ ]+msubr32[ ]+a2,a4,a6
248245
[ ]+.*:[ ]+.*[ ]+mulr64[ ]+a2,a4,a6
249246
[ ]+.*:[ ]+.*[ ]+mulsr64[ ]+a2,a4,a6

‎gas/testsuite/gas/riscv/insn-dsp.s‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -277,13 +277,10 @@ dsp:
277277
bitrevi a1, a2, 5
278278
wext a1, a2, a3
279279
wexti a1, a2, 5
280-
bpick a1, a2, a3, a4
281280
insb a1, a2, 2
282281

283282
# New Instructions in ZPSF
284283
maddr32 a2, a4, a6
285-
maxw a2, a4, a6
286-
minw a2, a4, a6
287284
msubr32 a2, a4, a6
288285
mulr64 a2, a4, a6
289286
mulsr64 a2, a4, a6

‎gas/testsuite/gas/riscv/insn-dsp64-zbpbo.d‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,9 @@ Disassembly of section .text:
99

1010
0+000 <dsp64>:
1111
[ ]+.*:[ ]+.*[ ]+cmix[ ]+a1,a2,a3,a4
12-
[ ]+.*:[ ]+.*[ ]+cmix[ ]+a0,a2,a1,a3
1312
[ ]+.*:[ ]+.*[ ]+fsrw[ ]+a1,a2,a3,a4
1413
[ ]+.*:[ ]+.*[ ]+max[ ]+a1,a2,a3
1514
[ ]+.*:[ ]+.*[ ]+min[ ]+a1,a2,a3
16-
[ ]+.*:[ ]+.*[ ]+max[ ]+a1,a2,a3
17-
[ ]+.*:[ ]+.*[ ]+min[ ]+a1,a2,a3
1815
[ ]+.*:[ ]+.*[ ]+pack[ ]+a1,a2,a3
1916
[ ]+.*:[ ]+.*[ ]+packu[ ]+a1,a2,a3
2017
[ ]+.*:[ ]+.*[ ]+pack[ ]+a1,a2,a3

‎gas/testsuite/gas/riscv/insn-dsp64-zbpbo.s‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,8 @@
11
dsp64:
22
cmix a1,a2,a3,a4
3-
bpick a0,a1,a3,a2
43
fsrw a1,a2,a3,a4
54
max a1,a2,a3
65
min a1,a2,a3
7-
maxw a1,a2,a3
8-
minw a1,a2,a3
96
pack a1,a2,a3
107
packu a1,a2,a3
118
pkbb32 a1,a2,a3

‎include/opcode/riscv-opc.h‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -634,8 +634,6 @@
634634
#define MASK_BITREV 0xfe00707f
635635
#define MATCH_BITREVI 0xe8000077
636636
#define MASK_BITREVI 0xfc00707f
637-
#define MATCH_BPICK 0x3077
638-
#define MASK_BPICK 0x600707f
639637
#define MATCH_CLRS8 0xae000077
640638
#define MASK_CLRS8 0xfff0707f
641639
#define MATCH_CLRS16 0xae800077
@@ -810,10 +808,6 @@
810808
#define MASK_MTLEI 0xfe00707f
811809
#define MATCH_MADDR32 0xc4001077
812810
#define MASK_MADDR32 0xfe00707f
813-
#define MATCH_MAXW 0xf2000077
814-
#define MASK_MAXW 0xfe00707f
815-
#define MATCH_MINW 0xf0000077
816-
#define MASK_MINW 0xfe00707f
817811
#define MATCH_MSUBR32 0xc6001077
818812
#define MASK_MSUBR32 0xfe00707f
819813
#define MATCH_MULR64 0xf0001077
@@ -1831,7 +1825,6 @@ DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64)
18311825
DECLARE_INSN(ave, MATCH_AVE, MASK_AVE)
18321826
DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV)
18331827
DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI)
1834-
DECLARE_INSN(bpick, MATCH_BPICK, MASK_BPICK)
18351828
DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8)
18361829
DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16)
18371830
DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32)
@@ -1918,8 +1911,6 @@ DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW)
19181911
DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL)
19191912
DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U)
19201913
DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32)
1921-
DECLARE_INSN(maxw, MATCH_MAXW, MASK_MAXW)
1922-
DECLARE_INSN(minw, MATCH_MINW, MASK_MINW)
19231914
DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32)
19241915
DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64)
19251916
DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64)

‎include/opcode/riscv.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -253,8 +253,6 @@ static const char * const riscv_pred_succ[16] =
253253
#define OP_SH_AQ 26
254254
#define OP_MASK_RL 0x1
255255
#define OP_SH_RL 25
256-
#define OP_MASK_RC 0x1f
257-
#define OP_SH_RC 27
258256

259257
#define OP_MASK_CSR 0xfffU
260258
#define OP_SH_CSR 20

‎opcodes/riscv-dis.c‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -346,10 +346,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
346346
char field_name[RVP_MAX_KEYWORD_LEN];
347347
if (parse_rvp_field (&d, field_name))
348348
{
349-
if (strcmp (field_name, "nds_rc") == 0)
350-
print (info->stream, "%s",
351-
riscv_gpr_names[EXTRACT_OPERAND (RC, l)]);
352-
else if (strcmp (field_name, "nds_rdp") == 0)
349+
if (strcmp (field_name, "nds_rdp") == 0)
353350
print (info->stream, "%s", riscv_gpr_names[rd]);
354351
else if (strcmp (field_name, "nds_rsp") == 0)
355352
print (info->stream, "%s", riscv_gpr_names[rs1]);

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