Cherrypick old cortex-m PRs #606
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Optimize critical_section: use MSR instruction
422: Add ITNS field to NVIC peripheral r=adamgreig a=sphw This PR adds the ITNS (Interrupt Target Non-secure) field to the NIVC peripheral. This field is required to write a boot loader for TrustZone-M devices, since it allows the user to use interrupts from non-secure states. I believe I have maintained the correct padding for the next fields, but I have not tested these changes on a non M33 device. So a close review and test would be appreciated. Co-authored-by: Sascha Wise <[email protected]>
Signed-off-by: Ariel D'Alessandro <[email protected]>
singleton: forward attributes
451: Small critical-section-related fixes. r=adamgreig a=Dirbaio See individual commit messages. Co-authored-by: Dario Nieuwenhuis <[email protected]>
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PRs backported:
PRs that we should still backport in this PR but I haven't got to yet:
LocalTimestampOptions, impl gatedTryFrom<u8>#366PRs that are breaking and we will probably want one day but can't include in 0.7.x:
SCB.ICSR.VECTACTIVEis 9 bits, not 8 #373&mut selfforrequest. #472Besides those listed above I don't think there are any PRs to the old cortex-m master branch between when we split it to 0.7.x (#375) and when we recently reverted it (#605).