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Merge pull request #838 from rust-embedded/const-default
use ConstZero instead of Default
2 parents 2a2b482 + 6b30ea5 commit e100619

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7 files changed

+46
-34
lines changed

7 files changed

+46
-34
lines changed

‎.github/workflows/ci.yml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
on:
22
push:
3-
branches: master
3+
branches: [master]
44
pull_request:
55
merge_group:
66

‎CHANGELOG.md

+1
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
88
## [Unreleased]
99

1010
- Generic `Periph<RB, A>`
11+
- use `ConstZero::ZERO` instead of `Default::default()` to force const
1112
- Add `mtvec_align` field to `riscv_config` to configure the byte alignment of interrupt vector table.
1213
- Fix reexport path when "%s" inside "derivedFrom"
1314
- Force using rust edition 2021 in CI

‎src/generate/generic.rs

+19-20
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,6 @@ impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
4949
/// Raw register type (`u8`, `u16`, `u32`, ...)
5050
pub trait RawReg:
5151
Copy
52-
+ Default
5352
+ From<bool>
5453
+ core::ops::BitOr<Output = Self>
5554
+ core::ops::BitAnd<Output = Self>
@@ -60,8 +59,10 @@ pub trait RawReg:
6059
{
6160
/// Mask for bits of width `WI`
6261
fn mask<const WI: u8>() -> Self;
63-
/// Mask for bits of width 1
64-
fn one() -> Self;
62+
/// `0`
63+
const ZERO: Self;
64+
/// `1`
65+
const ONE: Self;
6566
}
6667

6768
macro_rules! raw_reg {
@@ -71,10 +72,8 @@ macro_rules! raw_reg {
7172
fn mask<const WI: u8>() -> Self {
7273
$mask::<WI>()
7374
}
74-
#[inline(always)]
75-
fn one() -> Self {
76-
1
77-
}
75+
const ZERO: Self = 0;
76+
const ONE: Self = 1;
7877
}
7978
const fn $mask<const WI: u8>() -> $U {
8079
<$U>::MAX >> ($size - WI)
@@ -120,10 +119,10 @@ pub trait Writable: RegisterSpec {
120119
type Safety;
121120

122121
/// Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`
123-
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
122+
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
124123

125124
/// Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`
126-
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
125+
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
127126
}
128127

129128
/// Reset value of the register.
@@ -132,7 +131,7 @@ pub trait Writable: RegisterSpec {
132131
/// register by using the `reset` method.
133132
pub trait Resettable: RegisterSpec {
134133
/// Reset value of the register.
135-
const RESET_VALUE: Self::Ux;
134+
const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
136135

137136
/// Reset value of the register.
138137
#[inline(always)]
@@ -539,8 +538,8 @@ macro_rules! bit_proxy {
539538
/// Writes bit to the field
540539
#[inline(always)]
541540
pub fn bit(self, value: bool) -> &'a mut W<REG> {
542-
self.w.bits &= !(REG::Ux::one() << self.o);
543-
self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
541+
self.w.bits &= !(REG::Ux::ONE << self.o);
542+
self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
544543
self.w
545544
}
546545
/// Writes `variant` to the field
@@ -568,13 +567,13 @@ where
568567
/// Sets the field bit
569568
#[inline(always)]
570569
pub fn set_bit(self) -> &'a mut W<REG> {
571-
self.w.bits |= REG::Ux::one() << self.o;
570+
self.w.bits |= REG::Ux::ONE << self.o;
572571
self.w
573572
}
574573
/// Clears the field bit
575574
#[inline(always)]
576575
pub fn clear_bit(self) -> &'a mut W<REG> {
577-
self.w.bits &= !(REG::Ux::one() << self.o);
576+
self.w.bits &= !(REG::Ux::ONE << self.o);
578577
self.w
579578
}
580579
}
@@ -587,7 +586,7 @@ where
587586
/// Sets the field bit
588587
#[inline(always)]
589588
pub fn set_bit(self) -> &'a mut W<REG> {
590-
self.w.bits |= REG::Ux::one() << self.o;
589+
self.w.bits |= REG::Ux::ONE << self.o;
591590
self.w
592591
}
593592
}
@@ -600,7 +599,7 @@ where
600599
/// Clears the field bit
601600
#[inline(always)]
602601
pub fn clear_bit(self) -> &'a mut W<REG> {
603-
self.w.bits &= !(REG::Ux::one() << self.o);
602+
self.w.bits &= !(REG::Ux::ONE << self.o);
604603
self.w
605604
}
606605
}
@@ -613,7 +612,7 @@ where
613612
///Clears the field bit by passing one
614613
#[inline(always)]
615614
pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
616-
self.w.bits |= REG::Ux::one() << self.o;
615+
self.w.bits |= REG::Ux::ONE << self.o;
617616
self.w
618617
}
619618
}
@@ -626,7 +625,7 @@ where
626625
///Sets the field bit by passing zero
627626
#[inline(always)]
628627
pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
629-
self.w.bits &= !(REG::Ux::one() << self.o);
628+
self.w.bits &= !(REG::Ux::ONE << self.o);
630629
self.w
631630
}
632631
}
@@ -639,7 +638,7 @@ where
639638
///Toggle the field bit by passing one
640639
#[inline(always)]
641640
pub fn toggle_bit(self) -> &'a mut W<REG> {
642-
self.w.bits |= REG::Ux::one() << self.o;
641+
self.w.bits |= REG::Ux::ONE << self.o;
643642
self.w
644643
}
645644
}
@@ -652,7 +651,7 @@ where
652651
///Toggle the field bit by passing zero
653652
#[inline(always)]
654653
pub fn toggle_bit(self) -> &'a mut W<REG> {
655-
self.w.bits &= !(REG::Ux::one() << self.o);
654+
self.w.bits &= !(REG::Ux::ONE << self.o);
656655
self.w
657656
}
658657
}

‎src/generate/generic_atomic.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ mod atomic {
3939

4040
impl<REG: Readable + Writable> Reg<REG>
4141
where
42-
REG::Ux: AtomicOperations
42+
REG::Ux: AtomicOperations,
4343
{
4444
/// Set high every bit in the register that was set in the write proxy. Leave other bits
4545
/// untouched. The write is done in a single atomic instruction.
@@ -53,7 +53,7 @@ mod atomic {
5353
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
5454
{
5555
let bits = f(&mut W {
56-
bits: Default::default(),
56+
bits: REG::Ux::ZERO,
5757
_reg: marker::PhantomData,
5858
})
5959
.bits;
@@ -72,7 +72,7 @@ mod atomic {
7272
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
7373
{
7474
let bits = f(&mut W {
75-
bits: !REG::Ux::default(),
75+
bits: !REG::Ux::ZERO,
7676
_reg: marker::PhantomData,
7777
})
7878
.bits;
@@ -91,7 +91,7 @@ mod atomic {
9191
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
9292
{
9393
let bits = f(&mut W {
94-
bits: Default::default(),
94+
bits: REG::Ux::ZERO,
9595
_reg: marker::PhantomData,
9696
})
9797
.bits;

‎src/generate/generic_reg_vcell.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ impl<REG: Writable> Reg<REG> {
148148
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
149149
{
150150
let value = f(&mut W {
151-
bits: REG::Ux::default(),
151+
bits: REG::Ux::ZERO,
152152
_reg: marker::PhantomData,
153153
})
154154
.bits;
@@ -169,7 +169,7 @@ impl<REG: Writable> Reg<REG> {
169169
F: FnOnce(&mut W<REG>) -> T,
170170
{
171171
let mut writer = W {
172-
bits: REG::Ux::default(),
172+
bits: REG::Ux::ZERO,
173173
_reg: marker::PhantomData,
174174
};
175175

‎src/generate/register.rs

+14-7
Original file line numberDiff line numberDiff line change
@@ -413,24 +413,31 @@ pub fn render_register_mod(
413413

414414
let doc = format!("`write(|w| ..)` method takes [`{mod_ty}::W`](W) writer structure",);
415415

416-
let zero_to_modify_fields_bitmap = util::hex(zero_to_modify_fields_bitmap);
417-
let one_to_modify_fields_bitmap = util::hex(one_to_modify_fields_bitmap);
416+
let zero_to_modify_fields_bitmap = util::hex_nonzero(zero_to_modify_fields_bitmap)
417+
.map(|bm| quote!(const ZERO_TO_MODIFY_FIELDS_BITMAP: #rty = #bm;));
418+
let one_to_modify_fields_bitmap = util::hex_nonzero(one_to_modify_fields_bitmap)
419+
.map(|bm| quote!(const ONE_TO_MODIFY_FIELDS_BITMAP: #rty = #bm;));
418420

419421
mod_items.extend(quote! {
420422
#[doc = #doc]
421423
impl crate::Writable for #regspec_ty {
422424
type Safety = crate::#safe_ty;
423-
const ZERO_TO_MODIFY_FIELDS_BITMAP: #rty = #zero_to_modify_fields_bitmap;
424-
const ONE_TO_MODIFY_FIELDS_BITMAP: #rty = #one_to_modify_fields_bitmap;
425+
#zero_to_modify_fields_bitmap
426+
#one_to_modify_fields_bitmap
425427
}
426428
});
427429
}
428-
if let Some(rv) = properties.reset_value.map(util::hex) {
429-
let doc = format!("`reset()` method sets {} to value {rv}", register.name);
430+
if let Some(rv) = properties.reset_value.map(util::hex_nonzero) {
431+
let doc = if let Some(rv) = &rv {
432+
format!("`reset()` method sets {} to value {rv}", register.name)
433+
} else {
434+
format!("`reset()` method sets {} to value 0", register.name)
435+
};
436+
let rv = rv.map(|rv| quote!(const RESET_VALUE: #rty = #rv;));
430437
mod_items.extend(quote! {
431438
#[doc = #doc]
432439
impl crate::Resettable for #regspec_ty {
433-
const RESET_VALUE: #rty = #rv;
440+
#rv
434441
}
435442
});
436443
}

‎src/util.rs

+5
Original file line numberDiff line numberDiff line change
@@ -255,6 +255,11 @@ pub fn hex(n: u64) -> LitInt {
255255
)
256256
}
257257

258+
/// Turns non-zero `n` into an unsuffixed separated hex token
259+
pub fn hex_nonzero(n: u64) -> Option<LitInt> {
260+
(n != 0).then(|| hex(n))
261+
}
262+
258263
/// Turns `n` into an unsuffixed token
259264
pub fn unsuffixed(n: impl Into<u64>) -> LitInt {
260265
LitInt::new(&n.into().to_string(), Span::call_site())

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