Skip to content

Issues: rust-embedded/svd2rust

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

49 Open 239 Closed
49 Open 239 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

RISC-V settings file is not applied when using [email protected] and settings_file
#889 opened Nov 15, 2024 by jessebraham
Effect of VolatileCell's interior mutability on borrow checking
#888 opened Nov 14, 2024 by emmet-horgan
Whitespace in SVD files is lost
#858 opened Aug 18, 2024 by thejpster
4
Add (optional) doc_auto_cfg attribute to generated library
#855 opened Jun 25, 2024 by robamu
2
Build Errors in Code Generated from Renesas RA6M3 SVD
#852 opened Jun 18, 2024 by AddisonH
3
no_mangle on DEVICE_PERIPHERALS prevents optimizing write away
#833 opened Apr 1, 2024 by bauen1
Unclear how to use #[interrupt] macro without deprecated --reexport-interrupt flag
#830 opened Mar 26, 2024 by qwandor
3
No way to access w after writing
#827 opened Mar 19, 2024 by BigPeteB
1
feature: add bitfield operations for enumeratedValues generated types
#823 opened Mar 8, 2024 by rmsyn
3
thread 'main' panicked at src/util.rs:95:9: "...%s" is not a valid Ident
#811 opened Feb 14, 2024 by BrokenR3C0RD
2
Error generating psoc6_pac
#809 opened Feb 5, 2024 by dioguerra
4
/ci diff doesn't always catch action
#808 opened Feb 4, 2024 by Emilgardis
@Emilgardis
Is generated atomic register access correct?
#793 opened Dec 30, 2023 by 9names
1
Output Cargo.toml dependencies and features
#780 opened Nov 29, 2023 by Emilgardis
5
HDL to SVD?
#739 opened Jul 18, 2023 by rmsyn
2
[Corner Case] single bit field MT (Month Tens) of RTC should have u8 type rather a bool type enhancement
#719 opened May 29, 2023 by eZioPan
1
Unsafe register access option.
#714 opened Mar 10, 2023 by pellico
18
Disjoint array handling issue with Microchip SAM L21 bug
#713 opened Mar 4, 2023 by RavuAlHemio
2
Implement the ability to work with W outside of write
#708 opened Jan 27, 2023 by AndreySmirnov81
2
Without critical-section feature, Rust gets confused about missing take() enhancement
#704 opened Jan 3, 2023 by adamgreig
3
Custom write implementation for specific registers
#696 opened Nov 13, 2022 by G33KatWork
Why doesn't the CI use svd2rust-regress? enhancement
#689 opened Oct 29, 2022 by YuhanLiin
3
Identical enum names bug
#636 opened Jul 25, 2022 by burrbull
5
The ability to obtain offset values for the modifiable bit fields of registers
#582 opened Mar 14, 2022 by AndreySmirnov81
1
4
Add infrastructure to print diffs of outputs with a command enhancement
#550 opened Nov 9, 2021 by Emilgardis
1
ProTip! Find all open issues with in progress development work with linked:pr.