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Precompile: Frontend and backend for building circuits #799
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Suggestions for #799 Feel free to pick and choose from the suggestions. I talk about most of them on your PR. --------- Co-authored-by: dreamATD <[email protected]>
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First pass on gkr_iop
. It makes sense so far.
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Suggestions for #799 Feel free to pick and choose from the suggestions. I talk about most of them on your PR. --------- Co-authored-by: dreamATD <[email protected]>
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Awesome job!
I leave few comments in separate section due to large PR so I did the review in segmented time.
Most of the utility of code reused can be done later, I think the most important point might be trying one pre-compile (e.g. keccak-f) first, and benchmark the preliminary performance. Once it meet the requirements, we proceed to more engineering polishing works :)
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Suggestions for #799 Feel free to pick and choose from the suggestions. I talk about most of them on your PR. --------- Co-authored-by: dreamATD <[email protected]>
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related to #191 |
Suggestions for #799 Feel free to pick and choose from the suggestions. I talk about most of them on your PR. --------- Co-authored-by: dreamATD <[email protected]>
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Remove buffers and replace the underlying util functions. Add comments and fix some tiny bugs Suggestions for 'Frontend and backend for building circuits' (#801) Suggestions for #799 Feel free to pick and choose from the suggestions. I talk about most of them on your PR. --------- Co-authored-by: dreamATD <[email protected]> Refine according to comments refine the protocol prover and verifier structs Add more comments Tiny fix according to the latest comments.
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Some quick question
pub struct LayerWitness<E: ExtensionField> { | ||
pub bases: Vec<Vec<E::BaseField>>, | ||
pub exts: Vec<Vec<E>>, | ||
pub num_vars: usize, |
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same as above, could we make them all inDenseMultiliearPoly
format? with that we can make vector + num_vars in same structure
`keccakf` precompile + GKR-IOP integration
To close issue #632 named io as `debug_println` in guest program debug build, assuming no "println!" use case in guest program. In debug build, we extend stack address a bit to cover a reserved 256k for io. This extra reserved space also reflect in linker script, so the write to this region wont got any complaints from either elf or riscv emulator Besides, this PR also fix a previous problem where meaningful symbol in bss/sbss section will be skip due to their value are 0. We need to reserve and padding to cover them, since those might be some static variables initialized with 0 or uninitialized. Without do it, emulator will also complain regions is not writable. - cleanup previois workaround in guest program for io - extend stack address for io consistency check during debug build - refactor `load_elf` bss/sbss padding issue. - e2e command also shows io result. - respect profile in guest program examples compilation. An guest program with IO ```bash cargo run --release --features sanity-check --package ceno_zkvm --bin e2e -- --platform=ceno --hints=10 --public-io=4191 examples/target/riscv32im-ceno-zkvm-elf/release/examples/ceno_rt_io cargo run --features sanity-check --package ceno_zkvm --bin e2e -- --platform=ceno --hints=10 --public-io=4191 examples/target/riscv32im-ceno-zkvm-elf/debug/examples/ceno_rt_io ```
To close #936 ### Design rationales - introduce `VirtualPolynomialsBuilder` to lift a witness of "ArcPoly" type to expression container, so they can involve into expression domain for calculation - apply `VirtualPolynomialsBuilder` in tower prover. - keep scalar in base field as possible via introducing `Either<Base, Ext>` type - reserve design for "eq" degree -1 optimisation > this part work haven't done yet and set as future work :) `VirtualPolynomialsBuilder` is more like a util function for ceno main sumcheck flow. For GKR layer circuit in gk- iop #799 , the expression system will directly applied on chip-builder and skip `VirtualPolynomialsBuilder` ### benchmark there is no impact for e2e benchmark before/after this change, which is expected 2^20 ``` fibonacci_max_steps_1048576/prove_fibonacci/fibonacci_max_steps_1048576 time: [2.3583 s 2.3709 s 2.3848 s] change: [-1.8405% -1.0740% -0.2480%] (p = 0.03 < 0.05) Change within noise threshold. ``` 2^21 ``` fibonacci_max_steps_2097152/prove_fibonacci/fibonacci_max_steps_2097152 time: [4.4650 s 4.4758 s 4.4867 s] change: [-0.6673% -0.3122% +0.0493%] (p = 0.13 > 0.05) No change in performance detected. ``` 2^22 ``` fibonacci_max_steps_4194304/prove_fibonacci/fibonacci_max_steps_4194304 time: [9.0115 s 9.0574 s 9.1011 s] change: [-1.0658% -0.3407% +0.3803%] (p = 0.40 > 0.05) No change in performance detected. ```
sync up #799 with master
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### Change scope - [x] unify `Expression` with ceno - [x] unify sumcheck with ceno - [ ] WIP GKR witness generation, take bit benchmark as example --------- Co-authored-by: Zhang Zhuo <[email protected]>
``` RUST_LOG=info JEMALLOC_SYS_WITH_MALLOC_CONF=retain:true,metadata_thp:always,thp:always,dirty_decay_ms:-1,muzzy_decay_ms:-1,abort_conf:true cargo run --features jemalloc --package gkr_iop --bin lookup_keccak ``` > this only cover prover flow, and not verifier flow yet benchmark command ``` JEMALLOC_SYS_WITH_MALLOC_CONF=retain:true,metadata_thp:always,thp:always,dirty_decay_ms:-1,muzzy_decay_ms:-1,abort_conf:true cargo bench -p gkr_iop --features jemalloc --bench lookup_keccakf ``` Benchmark results on AMD EPYC 32 cores machine | Version | Throughput (keccak/s) | |------------------------|------------------------| | Ceno Keccak version | 4215 | | Plonky3 + Baby Bear | 1188.47 | | Plonky3 + Goldilocks | 683.05 | | Ceno (textbook gkr) | 128 | --------- Co-authored-by: Zhang Zhuo <[email protected]>
This is an implementation of the expression-based and plonkish-like GKR IOP protocol. The circuit is denoted as
Chip
, holding all information to process commit phases and GKR proving phase. In the current implementation, we assume there are two commit phases. To process the GKR phase, we extract aGKRCircuit
from it and run the GKR protocol. For the implementation status, the GKR phase is ready for review, while the commit phases hasn't been finalized.Define a GKR IOP protocol for a chip includes defining
build_commit_phase
,build_commit_phase2
andbuild_gkr_phase
. Specially,build_gkr_phase
is mainly to build GKR layers in the reverse order. In addition to specify the expressions, to simplify the case of either transferring evaluations from an input of a succeeding layer to an output of the current layer or even make some computations before feeding to the current layer, we use an evaluation tape to place the evaluations andEvalExpression
to define the computation. Each layer input will be assigned a position in the evaluation tape.EvalExpression
is defined as follows:of which the items denote how to compute the output evaluations. For more details please refer to gkr_iop/src/evaluation.rs.
Here are some subsequent tasks:
subprotocols/src/expression/
.Although the previous tasks should be done, I suggest to start the first round of review first. Would like to see comments from @naure and @hero78119 so that I can adjust the design before moving forward.
Upd: The design doc: https://hackmd.io/@sphere-liu/HyLR-h2L1g.