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…trollers in Scalasim
…trollers in Scalasim
Removed Arith from Structs
mattfel1
commented
Oct 31, 2020
| val idx = trues.head._2 | ||
| vals(idx).unbox | ||
| } | ||
| // else if (sels.exists{case Literal(true) => true; case _ => false}) { |
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can you remind me what was wrong with this?
mattfel1
commented
Oct 31, 2020
| emit(src"lazy val w$i = Access(${w.hashCode}, ${w.port.muxPort}, ${w.port.muxOfs}, ${w.port.castgroup.mkString("List(",",",")")}, ${w.port.broadcast.mkString("List(",",",")")}, ${w.shiftAxis}, PortInfo(${w.port.bufferPort}, ${1 max w.accessWidth}, ${1 max ofsWidth}, ${banksWidths.map(1 max _).mkString("List(",",",")")}, ${bitWidth(mem.tp.typeArgs.head)}, $resids))") | ||
| } | ||
| if (mem.writers.isEmpty) {emit(src"val w0 = AccessHelper.singular(32)")} | ||
| if (mem.writers.isEmpty) {emit(src"lazy val w0 = AccessHelper.singular(32)")} |
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what is the advantage of making these lazy vals?
mattfel1
commented
Oct 31, 2020
| warn(s"Detected potential write conflicts on ${a.access.ctx} (uid: ${a.unroll}) and ${conflicts.head.access.ctx} (uid: ${conflicts.head.unroll}) to memory ${mem.ctx} (${mem.name.getOrElse("")})") | ||
| warn(s" These are technically unbankable but you signed the waiver (by adding .conflictable) that says you know what you are doing") | ||
| // warn(s"Detected potential write conflicts on ${a.access.ctx} (uid: ${a.unroll}) and ${conflicts.head.access.ctx} (uid: ${conflicts.head.unroll}) to memory ${mem.ctx} (${mem.name.getOrElse("")})") | ||
| // warn(s" These are technically unbankable but you signed the waiver (by adding .conflictable) that says you know what you are doing") |
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were these warns removed on purpose?
mattfel1
commented
Oct 31, 2020
src/spatial/util/modeling.scala
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| readsAfter.foreach{r => | ||
| val dist = paths(regWrite).toInt - paths(r).toInt | ||
| warn(s"Avoid reading register (${reg.name.getOrElse("??")}) after writing to it in the same inner loop, if this is not an accumulation (write: ${regWrite.ctx}, read: ${r.ctx})") | ||
| // warn(s"Avoid reading register (${reg.name.getOrElse("??")}) after writing to it in the same inner loop, if this is not an accumulation (write: ${regWrite.ctx}, read: ${r.ctx})") |
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removed temporarily to prevent spam?
mattfel1
commented
Oct 31, 2020
| assert(getArg(z0) == 3) | ||
| assert(getArg(z1) == 5) | ||
| } | ||
| } No newline at end of file |
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this test is already in VecTypes.scala in master so this file can be dropped
mattfel1
commented
Oct 31, 2020
| val otherUInt: UInt = other.asUInt | ||
| vec := otherUInt.asTypeOf(vec) | ||
| } | ||
| } |
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If I understand correctly, this means we can change my recent update for vecs in structs:
case FieldApply(struct, field) =>
emit(createWire(quote(lhs),remap(lhs.tp)))
val (start, end) = getField(struct.tp, field)
lhs.tp match {
case v: Vec[_] => emit(src"$lhs.toSeq.zipWithIndex.foreach{case (fa, i) => fa := $struct($start, $end + (${v.size - 1} - i) * ${bitWidth(v.typeArgs.head)})}")
case _ => emit(src"$lhs.r := $struct($start, $end)")
}
to just $lhs := $struct($start, $end) for the case of a Vec field?
Or is this UIntlike trait used in a different way somewhere that I missed?
# Conflicts: # fringe/src/fringe/utils/implicits.scala
…s' into issue313_chiselgen_vec_chiselvecs # Conflicts: # test/spatial/tests/compiler/VecInStruct.scala
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