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serial: set active state level for RX and TX pins #203

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serial: set active state level for RX and TX pins #203

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serial: set active state level for RX and TX pins
maximeborges Oct 2, 2023
7ddccb2
Merge branch 'main' into usart/inversion
maximeborges Dec 4, 2023
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30 changes: 27 additions & 3 deletions src/serial.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -187,10 +187,20 @@ where
let ch = config.character_match.unwrap_or(0);
usart.cr2.write(|w| w.add().bits(ch));

// Set active state level for RX and TX pins
usart.cr2.modify(|_r, w| {
match config.active_level_tx {
ActiveLevel::Standard => w.txinv().clear_bit(),
ActiveLevel::Inverted => w.txinv().set_bit(),
};
match config.active_level_rx {
ActiveLevel::Standard => w.rxinv().clear_bit(),
ActiveLevel::Inverted => w.rxinv().set_bit(),
}
});

// Enable tx / rx, configure data bits and parity
usart.cr1.modify(|_, w| {
w.te().enabled().re().enabled().ue().enabled();

// M[1:0] are used to set data bits
// M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
// M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
Expand All @@ -205,7 +215,9 @@ where
Parity::ParityEven => w.ps().even().pce().enabled(),
Parity::ParityOdd => w.ps().odd().pce().enabled(),
Parity::ParityNone => w.pce().disabled(),
}
};

w.te().enabled().re().enabled().ue().enabled();
});

// Enable DMA
Expand Down Expand Up @@ -457,6 +469,16 @@ pub struct Config {
pub sysclock: bool,
pub parity: Parity,
pub data_bits: DataBits,
pub active_level_tx: ActiveLevel,
pub active_level_rx: ActiveLevel,
}

/// Active level on the wire
pub enum ActiveLevel {
/// Idle = high (VDD); Active = low (GND)
Standard,
/// Inverted: Idle = low (GND); Active = high (VDD)
Inverted,
}

pub enum Oversampling {
Expand Down Expand Up @@ -497,6 +519,8 @@ impl Default for Config {
sysclock: false,
parity: Parity::ParityNone,
data_bits: DataBits::Bits8,
active_level_tx: ActiveLevel::Standard,
active_level_rx: ActiveLevel::Standard,
}
}
}
Expand Down