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Support partial vector extension instructions #545

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Support partial vector extension instructions #545

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fbcfad1
Add decode for RISC-V "V" Vector extension
vestata Dec 17, 2024
c4725d5
Implement vector configuration intructions
vestata Jan 9, 2025
7edf398
Implement basic unit-stride vector load/store
vestata Jan 12, 2025
c3374ea
Modularize single-width vector instruction
vestata Jan 17, 2025
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10 changes: 10 additions & 0 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -142,6 +142,16 @@ $(call set-feature, EXT_C)
ENABLE_RV32E ?= 0
$(call set-feature, RV32E)

# Vector extension instructions
ENABLE_EXT_V ?= 0
$(call set-feature, EXT_V)
VLEN ?= 128 # Default VLEN is 128
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Shall this moved into the conditional block of ifeq ($(call has, EXT_V), 1) ?

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You're right. I'll move VLEN ?= 128 into the conditional block. Thanks for pointing that out.

ifeq ($(call has, EXT_V), 1)
CFLAGS += -DVLEN=$(VLEN)
ENABLE_EXT_F ?= 1
$(call set-feature, EXT_F)
endif

# Control and Status Register (CSR)
ENABLE_Zicsr ?= 1
$(call set-feature, Zicsr)
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