[NVIDIA] Lower tensor-map proxy fences with NVVM#10940
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Summary
Replace the remaining supported compiler-generated inline NVIDIA fence with NVVM dialect operations.
The tensor-map acquire fence currently emits
fence.proxy.tensormap::generic.acquire.gputhrough inline PTX. Keeping this operation in NVVM exposes its synchronization semantics to MLIR and delegates PTX spelling and target validation to LLVM's NVPTX backend.Details
fence.proxy.tensormap::generic.acquire.gpuwithnvvm.fence.proxy.acquire.cp.async.bulkPTXAS workaround unchanged.Other compiler-generated fence paths already use structured lowering:
nvvm.fence.proxy;fence.sc.clusterpath.tensormap.cp_fenceproxyremains inline because the pinned LLVM revision has no corresponding NVVM operation or LLVM intrinsic. It is a tensor-map copy instruction and requires LLVM support before it can be migrated.At Triton's pinned LLVM revision, the NVPTX backend maps the new operation to the same
fence.proxy.tensormap::generic.acquire.gpuPTX instruction.Testing
pre-commit run --from-ref origin/main --to-ref HEADmakelit -v test/Conversion(81/81 passed)llcand assembled it with CUDA 13.3ptxasfor SM90 and SM100a.New contributor declaration
I am not making a trivial change, such as fixing a typo in a comment.
I have written a PR description following these
rules.
I have run
pre-commit run --from-ref origin/main --to-ref HEAD.I have added tests.
/testforlittests/unittestfor C++ tests/python/testfor end-to-end testsI have not added any
littests.