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PR switches shr (bitwise right shift) usage to eshr (emulated bitwise right shift) to ensure that signed types are properly dispatched to asr (arithmetic right shift).

@echeresh echeresh added the platform:gpu-intel Codeowner: @oneapi-src/onednn-gpu-intel label Oct 15, 2025
@echeresh echeresh requested a review from a team as a code owner October 15, 2025 01:30
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make test
set test_scope=NIGHTLY
disable test_device_cpu
disable benchdnn_all
enable benchdnn_conv
enable benchdnn_deconv
enable benchdnn_reorder
enable benchdnn_pool
enable arch_gpu_xe-hpc
enable arch_gpu_xe-hpg-atsm
enable arch_gpu_xe-hpg-dg2
enable arch_gpu_xe-lp
enable arch_gpu_xe-lpg
enable arch_gpu_xe-lpg+
enable arch_gpu_xe2-hpg-bmg
enable arch_gpu_xe2-lpg
enable arch_gpu_xe3-lpg

mach(1, _qot, _x, m);
shr<uint32_t>(1, _qot, _qot, p - 32);
// qot = (x * m) >> p
bool use_mach = true;
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nit: const to prevent a coverity complaint

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This variable is updated in embargo code so it has to be non-const. Can I add // NOLINT comment to ignore that?

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We can just dismiss the coverity hit later.

template <typename DT = void>
void eshr(const ngen::InstructionModifier &mod, ngen::RegData dst,
ngen::RegData src0, ngen::RegData src1) {
bool is_q = ngen_is_qw(src0.getType());
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nit: same here

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Thanks, fixed.

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3 participants