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Verilog to Routing

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  1. vtr-verilog-to-routing vtr-verilog-to-routing Public

    Verilog to Routing -- Open Source CAD Flow for FPGA Research

    C++ 1.1k 422

Repositories

Showing 7 of 7 repositories
  • vtr-verilog-to-routing Public

    Verilog to Routing -- Open Source CAD Flow for FPGA Research

    verilog-to-routing/vtr-verilog-to-routing’s past year of commit activity
    C++ 1,123 422 113 (2 issues need help) 55 Updated Jul 25, 2025
  • ezgl Public
    verilog-to-routing/ezgl’s past year of commit activity
    C++ 10 Apache-2.0 7 0 1 Updated Jul 23, 2025
  • verilog-to-routing.github.io Public

    Website for Verilog to Routing

    verilog-to-routing/verilog-to-routing.github.io’s past year of commit activity
    SCSS 6 3 0 4 Updated May 30, 2025
  • libblifparse Public

    Parsing library for BLIF netlists

    verilog-to-routing/libblifparse’s past year of commit activity
    C++ 19 MIT 11 2 2 Updated Nov 1, 2024
  • tatum Public

    Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

    verilog-to-routing/tatum’s past year of commit activity
    C++ 62 MIT 11 3 1 Updated May 28, 2024
  • libsdcparse Public
    verilog-to-routing/libsdcparse’s past year of commit activity
    C++ 12 MIT 7 2 1 Updated Jan 29, 2020
  • vtr-buildbot Public

    Buildbot Infrastructure for VTR

    verilog-to-routing/vtr-buildbot’s past year of commit activity
    HTML 6 5 0 0 Updated Dec 12, 2019

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