Skip to content

vipul43/RISC_V_architecture_design

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

9 Commits
i, r, ld, s, b type instructions(no counters)
i, r, ld, s, b type instructions(no counters)
 
 
i, r, ld, s, b, uj type instructions(using counters)
i, r, ld, s, b, uj type instructions(using counters)
 
 
i_type and r_type together
i_type and r_type together
 
 
i_type instructions
i_type instructions
 
 
i_type, r_type(including ^, |, &, <<, >>, >>>), load and store instructions(no counters)
i_type, r_type(including ^, |, &, <<, >>, >>>), load and store instructions(no counters)
 
 
i_type, r_type(including ^, |, &, <<, >>, >>>), load and store instructions(using counters)
i_type, r_type(including ^, |, &, <<, >>, >>>), load and store instructions(using counters)
 
 
r_type instructions
r_type instructions
 
 
.DS_Store
.DS_Store
 
 
LICENSE
LICENSE
 
 
README.md
README.md
 
 

Repository files navigation

RISC-V-architecture-design

#designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE #each folder contains corresponding source files, input and output files, and screenshots of simulations

About

designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE

Topics

controlpathdatapathhennessy-and-pattersonrisc-varchitectureriscv64verilog-hdlxilinx-vivado

Resources

Readme
MIT license
Activity

Stars

1 star

Watchers

1 watching

Forks

1 fork
Report repository

Releases

Packages

Contributors

Languages