EX-14041 Zero-Valued Jobstats Metrics Should Be Skipped#134
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…-Valued Jobstats Metrics Should Be Skipped
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Bencher Report| Branch | ddn-ajagdhane/EX-14041 |
| Testbed | ci-runner |
Click to view all benchmark results
| Benchmark | Latency | Benchmark Result nanoseconds (ns) (Result Δ%) | Lower Boundary nanoseconds (ns) (Limit %) | Upper Boundary nanoseconds (ns) (Limit %) |
|---|---|---|---|---|
| parse_benchmarks/combine_performance | 📈 view plot 🚷 view threshold | 123,430,000.00 ns(-59.87%)Baseline: 307,553,846.15 ns | -881,509,483.80 ns (-714.18%) | 1,496,617,176.11 ns (8.25%) |
Codecov Report❌ Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## main #134 +/- ##
==========================================
- Coverage 94.40% 94.21% -0.20%
==========================================
Files 44 44
Lines 5681 5683 +2
Branches 5681 5683 +2
==========================================
- Hits 5363 5354 -9
- Misses 245 263 +18
+ Partials 73 66 -7
Flags with carried forward coverage won't be shown. Click here to find out more. ☔ View full report in Codecov by Sentry. 🚀 New features to boost your workflow:
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| Branch | ddn-ajagdhane/EX-14041 |
| Testbed | ci-runner |
⚠️ WARNING: No Threshold found!Without a Threshold, no Alerts will ever be generated.
- RAM Hits (hits)
- DLmr (misses (reads))
- Dr (reads)
- I1mr (misses (reads))
- ILmr (misses (reads))
- L1 Hits (hits)
- Total read+write (reads/writes)
- LLi Miss Rate (misses (%))
- RAM Hit Rate (hits (%))
- LL Hits (hits)
- LLd Miss Rate (misses (%))
- D1mr (misses (reads))
- L1 Hit Rate (hits (%))
- Dw (writes)
- Estimated Cycles (cycles)
- DLmw (misses (writes))
- LL Hit Rate (hits (%))
- D1mw (misses (writes))
- I1 Miss Rate (misses (%))
- LL Miss Rate (misses (%))
- D1 Miss Rate (misses (%))
Click here to create a new Threshold
For more information, see the Threshold documentation.
To only post results if a Threshold exists, set the--ci-only-thresholdsflag.
Click to view all benchmark results
| Benchmark | D1 Miss Rate | misses (%) | D1mr | misses (reads) x 1e3 | D1mw | misses (writes) x 1e3 | DLmr | misses (reads) | DLmw | misses (writes) x 1e3 | Dr | reads x 1e6 | Dw | writes x 1e6 | Estimated Cycles | cycles x 1e6 | I1 Miss Rate | misses (%) | I1mr | misses (reads) x 1e3 | ILmr | misses (reads) | Instructions | Benchmark Result instructions x 1e6 (Result Δ%) | Lower Boundary instructions x 1e6 (Limit %) | Upper Boundary instructions x 1e6 (Limit %) | L1 Hit Rate | hits (%) | L1 Hits | hits x 1e6 | LL Hit Rate | hits (%) | LL Hits | hits x 1e3 | LL Miss Rate | misses (%) | LLd Miss Rate | misses (%) | LLi Miss Rate | misses (%) | RAM Hit Rate | hits (%) | RAM Hits | hits x 1e3 | Total read+write | reads/writes x 1e6 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| lustre_metrics::memory_benches::bench_encode_lustre_metrics with_setup:generate_records() | 📈 view plot | 0.93 % | 📈 view plot | 24.99 reads x 1e3 | 📈 view plot | 9.15 writes x 1e3 | 📈 view plot | 116.00 reads | 📈 view plot | 6.44 writes x 1e3 | 📈 view plot | 2.46 x 1e6 | 📈 view plot | 1.23 x 1e6 | 📈 view plot | 14.80 x 1e6 | 📈 view plot | 0.01 % | 📈 view plot | 1.05 reads x 1e3 | 📈 view plot | 887.00 reads | 📈 view plot 🚷 view threshold | 10.75 x 1e6(-24.02%)Baseline: 14.15 x 1e6 | 1.75 x 1e6 (16.24%) | 26.55 x 1e6 (40.49%) | 📈 view plot | 99.76 % | 📈 view plot | 14.40 x 1e6 | 📈 view plot | 0.19 % | 📈 view plot | 27.75 x 1e3 | 📈 view plot | 0.05 % | 📈 view plot | 0.18 % | 📈 view plot | 0.01 % | 📈 view plot | 0.05 % | 📈 view plot | 7.44 x 1e3 | 📈 view plot | 14.44 x 1e6 |
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