EX-13898: Add support for Lustre Quota Aggregation (LQA)#149
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Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## main #149 +/- ##
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+ Coverage 94.57% 94.61% +0.03%
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Files 46 46
Lines 6107 6150 +43
Branches 6107 6150 +43
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+ Hits 5776 5819 +43
Misses 256 256
Partials 75 75
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Bencher Report| Branch | xyang/EX-13898 |
| Testbed | ci-runner |
Click to view all benchmark results
| Benchmark | Latency | Benchmark Result milliseconds (ms) (Result Δ%) | Lower Boundary milliseconds (ms) (Limit %) | Upper Boundary milliseconds (ms) (Limit %) |
|---|---|---|---|---|
| jobstats 100 | 📈 view plot 🚷 view threshold | 1.51 ms(+2.18%)Baseline: 1.48 ms | 1.32 ms (87.21%) | 1.64 ms (92.15%) |
| jobstats 1000 | 📈 view plot 🚷 view threshold | 14.53 ms(+1.51%)Baseline: 14.32 ms | 12.76 ms (87.82%) | 15.87 ms (91.57%) |
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| Branch | xyang/EX-13898 |
| Testbed | ci-runner |
⚠️ WARNING: No Threshold found!Without a Threshold, no Alerts will ever be generated.
- L1 Hit Rate (hits (%))
- I1 Miss Rate (misses (%))
- DLmw (misses (writes))
- I1mr (misses (reads))
- LL Hits (hits)
- L1 Hits (hits)
- Estimated Cycles (cycles)
- LLd Miss Rate (misses (%))
- RAM Hit Rate (hits (%))
- Total read+write (reads/writes)
- D1mr (misses (reads))
- Dr (reads)
- D1mw (misses (writes))
- Dw (writes)
- DLmr (misses (reads))
- LL Miss Rate (misses (%))
- LLi Miss Rate (misses (%))
- RAM Hits (hits)
- D1 Miss Rate (misses (%))
- LL Hit Rate (hits (%))
- ILmr (misses (reads))
Click here to create a new Threshold
For more information, see the Threshold documentation.
To only post results if a Threshold exists, set the--ci-only-thresholdsflag.
Click to view all benchmark results
| Benchmark | D1 Miss Rate | misses (%) | D1mr | misses (reads) x 1e3 | D1mw | misses (writes) x 1e3 | DLmr | misses (reads) | DLmw | misses (writes) x 1e3 | Dr | reads x 1e6 | Dw | writes x 1e6 | Estimated Cycles | cycles x 1e6 | I1 Miss Rate | misses (%) | I1mr | misses (reads) x 1e3 | ILmr | misses (reads) | Instructions | Benchmark Result instructions x 1e6 (Result Δ%) | Lower Boundary instructions x 1e6 (Limit %) | Upper Boundary instructions x 1e6 (Limit %) | L1 Hit Rate | hits (%) | L1 Hits | hits x 1e6 | LL Hit Rate | hits (%) | LL Hits | hits x 1e3 | LL Miss Rate | misses (%) | LLd Miss Rate | misses (%) | LLi Miss Rate | misses (%) | RAM Hit Rate | hits (%) | RAM Hits | hits x 1e3 | Total read+write | reads/writes x 1e6 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| lustre_metrics::memory_benches::bench_encode_lustre_metrics with_setup:generate_records() | 📈 view plot | 0.92 % | 📈 view plot | 25.30 reads x 1e3 | 📈 view plot | 9.06 writes x 1e3 | 📈 view plot | 123.00 reads | 📈 view plot | 6.39 writes x 1e3 | 📈 view plot | 2.48 x 1e6 | 📈 view plot | 1.24 x 1e6 | 📈 view plot | 14.86 x 1e6 | 📈 view plot | 0.01 % | 📈 view plot | 1.07 reads x 1e3 | 📈 view plot | 920.00 reads | 📈 view plot 🚷 view threshold | 10.77 x 1e6(-19.35%)Baseline: 13.35 x 1e6 | 2.43 x 1e6 (22.52%) | 24.28 x 1e6 (44.36%) | 📈 view plot | 99.76 % | 📈 view plot | 14.46 x 1e6 | 📈 view plot | 0.19 % | 📈 view plot | 28.00 x 1e3 | 📈 view plot | 0.05 % | 📈 view plot | 0.17 % | 📈 view plot | 0.01 % | 📈 view plot | 0.05 % | 📈 view plot | 7.43 x 1e3 | 📈 view plot | 14.49 x 1e6 |
Signed-off-by: Xiao Yang <xyang@ddn.com>
breuhan
approved these changes
Jul 9, 2026
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