Risc-V experiments on Arty A7

links

Tools

• chisel bootcamp
• chisel homepage

Arty A7 Risc-V Tutorials

• DigiKey
• Digilent
• SiFive

Hints

identify USB devices

get mapping information via

$ ls -l /dev/serial/by-id
total 0
lrwxrwxrwx 1 root root 13 Feb 13 20:17 usb-15ba_Olimex_OpenOCD_JTAG_ARM-USB-TINY-H_OL9533D9-if01-port0 -> ../../ttyUSB2
lrwxrwxrwx 1 root root 13 Feb 13 20:17 usb-Digilent_Digilent_USB_Device_210319AFEE0C-if01-port0 -> ../../ttyUSB1

Level 0 - FPGA test

To check basic function of the Toolset and the FPGA board ..

.. build the Xilinx docker image

$ cd docker/xilinx
$ <download Vivado webpack installer>
$ ./Xilinx_Unified_2020.2_1118_1232_Lin64.bin -- --batch AuthTokenGen
$ cp ~/.Xilinx/wi_authentication_key .
$ ./build.sh

.. start an interactive docker session and build the vivado_getting_started project in Vivado

$ docker/xilinx/run.sh
$ vivado

Level 1 - run "Hello World" on synthesized E310 core

prepare tools

build the docker image with the SiFive toolchain

$ cd docker/risc-v
$ ./build.sh

build verilog and synthesize design

If using the Arty A7 100 Board set the board type accordingly

diff --git a/Makefile.e300artydevkit b/Makefile.e300artydevkit
index 110c08a..3476a60 100644
--- a/Makefile.e300artydevkit
+++ b/Makefile.e300artydevkit
@@ -6,7 +6,7 @@ MODEL := E300ArtyDevKitFPGAChip
 PROJECT := sifive.freedom.everywhere.e300artydevkit
 export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
 export CONFIG := E300ArtyDevKitConfig
-export BOARD := arty
+export BOARD := arty_a7_100
 export BOOTROM_DIR := $(base_dir)/bootrom/xip
 
 rocketchip_dir := $(base_dir)/rocket-chip

Run the risc-v docker image and build the verilog sources from the chisel sources:

$ docker/risc-v/run.sh
$ . clean.sh
$ cd sifive-freedom
$ make -f Makefile.e300artydevkit verilog

The verilog should be in builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v

Synthesize the verilog for the FPGA (still in the risc-v docker)

$ make -f Makefile.e300artydevkit mcs

after which the output is in builds/e300artydevkit/obj.

Program the FPGA:

1. Open Vivado, go to "Flow -> Open Hardware Manager"
2. "Open Target -> Auto connect"
3. select device xc7a100t_0, right click "Add Configuration Memory Device" and select alias s25fl127s-spi-x1_x2_x4
4. select OK when asked if you want to program the configuration and select the .mcs from the obj directory
5. when programming the FPGA was successful, press the "PROG" button on the FPGA board

build the Hello World

1. connect the Olimex to JD of the FPGA board (see the adapter in the pcb directory)
2. change to the freedom-e-sdk directory
3. upgrade typed-ast to 1.5.x in requirements.txt (the python version in the docker image is too recent and no typed-ast package exists for it on pypi.org)
4. make BSP=metal PROGRAM=hello TARGET=freedom-e310-arty clean
5. make BSP=metal PROGRAM=hello TARGET=freedom-e310-arty software
6. make BSP=metal PROGRAM=hello TARGET=freedom-e310-arty upload
7. tio /dev/ttyUSB0 -b 57600 should show "Hello World!" now

Level 2 - remote FPGA programming

An old Asus eee pc is often used on my lab bench to control powersupplies or log data from measurement instruments. I tend to connect the FPGA board to it too. However, its CPU and RAM are too tiny to run Vivado at reasonable speed. But it can run Vivavdos hw_server without problems.

On the lab PC run

$ docker/risc-v/run.sh
$ /tools/Xilinx/Vivado/2021.2/bin/hw_server

Start the hardware manager on the Vivado workstation and connect to the lab PC.