drivers: stm32 qspi flash driver enables the MemoryMapped mode #61122

FRASTM · 2023-08-03T14:28:48Z

This PR is enabling the MemoryMapped to access the qua NOR flash at the end of the initialization.
With this configuration, the NOR flash access is done with memcopy in read or write
Note that the erase is not supported but writing is possible in MemoryMapped mode.
(It is not recommended to fill the memory with 0xFFFFFFFF)

"QSPI NOR devices are often used for read-only applications in memory mapped mode. And when the program instructions are executed directly from the flash memory, this is known as Execute in Place or XIP mode."

The drivers detects the CONFIG_STM32_MEMMAP flag to enable the MemoryMapped mode.

Requires PR #61082

FRASTM · 2023-08-07T08:55:08Z

After running the samples/drivers/spi_flash, reading the quad NOR flash of the stm32h747_disco_m7 in MemoryMapped mode gives the

Perform test on single sector


Data read : 
000ff000  read 55
000ff001  read aa
000ff002  read 66
000ff003  read 99
000ff004  read ff
000ff005  read ff
000ff006  read ff
000ff007  read ff

zephyrbot · 2023-08-07T13:13:07Z

The following west manifest projects have been modified in this Pull Request:

Name	Old Revision	New Revision	Diff

Note: This message is automatically posted and updated by the Manifest GitHub Action.

FRASTM · 2023-08-11T14:37:15Z

rebase on e9dd938

GeorgeCGV · 2023-08-15T10:22:56Z

soc/arm/st_stm32/stm32h7/mpu_regions.c

+					REGION_RAM_ATTR(REGION_SRAM_SIZE)),
+	MPU_REGION_ENTRY("QSPI", 0x90000000,
+					REGION_EXTMEM_ATTR(REGION_256M)),


What is the point of having it in stm32h7.dtsi as RAM and here as EXTMEM?

Questioning out of curiosity.

dts/arm/st/h7/stm32h7.dtsi

erwango · 2023-08-30T15:16:16Z

@benjaminbjornsson FYI

FRASTM · 2023-09-06T09:36:46Z

New version where the HAL is not changed thanks to direct access to the hqspi instance in the flash_stm32_qspi driver
The flash base address and size are directly placed in the flash-controller node of the Device Tree : reg = <0x90000000 DT_SIZE_M(64)>; (no more size property required)

One common commit 8320167aecb8f74816714150099cf883df86ded0 with #61082

Add the memory region to map the external NOR flash

Tested with the stm32h747i_disco_m7 disco board ; using a sample to demonstrate the read operation in memorymapped mode (no erase but writing a few bytes) :

erwango · 2023-08-29T14:17:47Z

drivers/flash/Kconfig.stm32

@@ -70,4 +70,11 @@ config FLASH_STM32_BLOCK_REGISTERS
 	  registers improves system security, because flash content (or
 	  protection settings) can't be changed even when exploit was found.

+config STM32_XIP


We need some more explicit name for this option. Usual STM32 config on internal flash is XIP (CONFIG_XIP=y).
STM32_EXT_MEM_XIP, STM32_MEM_MAPPED, ...

erwango · 2023-09-07T17:10:32Z

drivers/flash/flash_stm32_qspi.c

+#ifdef CONFIG_STM32_XIP
+
+/* Function to return true if the quad-NOR flash is in MemoryMapped else false */
+static bool qspi_is_memorymapped(const struct device *dev)


According to HAL team, we should be able to use the HAL_GetStatus API.

According to HAL team, we should be able to use the HAL_GetStatus API.

Update: This won't work as HAL_GetStatus() is based on driver internal variable (reset when switching from MCUBoot to Zephyr application), not hw setting. qspi_is_memorymapped is indeed actually required.

FRASTM · 2023-09-15T14:50:02Z

Cannot read the QSPI flash correctly
(gdb) x /8x 0x90000000
0x90000000: 0x0000f33d 0x00360000 0x00000000 0x00000000
0x90000010: 0x00000000 0x00000000 0x00000000 0x00000000
0x90000020: 0x00000000 0x00000000 0x00000000 0x00000000
0x90000030: 0x00000000 0x00000000 0x00000000 0x00000000

when the STM32CubeProgrammer gives
0x90000000: 96F3B83D 00000000 00000400 00003B36

For the flash driver, the base address is the MCU internal flash address (usualyy 0x8000000). This PR gets the that address from the device tree node "st,stm32-nv-flash" instead of relying on the CONFIG_FLASH_BASE_ADDRESS which might differ when building for another flash memory. Signed-off-by: Francois Ramu <[email protected]>

This CONFIG_STM32_MEMMAP is for enabling the MemoryMapped mode on external octo or quad spi memory. In this case, the flash_stm32_read is done in mem map mode the flash_stm32_erase is not available. Signed-off-by: Francois Ramu <[email protected]>

Enable the MemoryMapped Mode for the stm32 octoFlash driver Configure the Flash in MemoryMapped to use in XiP mode. With this mode the erase and write are not supported. Address and size are given by the DTS register property. Signed-off-by: Francois Ramu <[email protected]>

This change is aborting the memoryMapped mode of the octo-flash before erasing or writing the NOR. Operations are performed in command mode. Reading is always performed in MemoryMapped mode (memcopy) Signed-off-by: Francois Ramu <[email protected]>

Enable the DCACHE1 in INCR burt mode to allow writing to the external NOR octoFlash when in MemoryMapped mode Signed-off-by: Francois Ramu <[email protected]>

Define the Device tree of the b_u585i_iot02a disco kit to access the external NOR octo-flash in MemoryMapped mode for XiP Signed-off-by: Francois Ramu <[email protected]>

Gives a sample to execute the little fs on external memory map (XiP) where the lfs1 partition is in internal mcu flash The application is built/linked/stored in the external NOR flash on slot1 partition. Signed-off-by: Francois Ramu <[email protected]>

Skip the PLL1 init if it is already running, this will avoid disabling the PLL when running after a jump from mcuboot Signed-off-by: Francois Ramu <[email protected]>

Define the MPU attribute to be ATTR_MPU_IO for the qspi region, starting at 0x90000000 of the stm32h7 serie. Signed-off-by: Francois Ramu <[email protected]>

Define the Device tree of the stm32h7b3i_dk disco board to access the external NOR octo-flash in MemoryMapped mode for XiP Set openocd runner for debugging. Signed-off-by: Francois Ramu <[email protected]>

Gives a sample to execute the little fs on external memory map (XiP) where the lfs1 partition is in internal mcu flash Signed-off-by: Francois Ramu <[email protected]>

Configures the external NOR Flash in MemoryMapped Mode, at the end of the NOR flash-controller initialization. Then reading/writing are performed in MemoryMapped mode with memcopy (and no more with command mode). In this mode: erasing is not supported anymore. The flash size and address are given by the DTS <reg> property. Signed-off-by: Francois Ramu <[email protected]>

Configure the quad-spi in DualFlash Mode when enabling the MemoryMapped then reading is possible with memcopy. Signed-off-by: Francois Ramu <[email protected]>

Define the Device tree of the stm32l496g_disco board or stm32h750b disco kit to access the external NOR quad-flash in MemoryMapped mode for XiP Signed-off-by: Francois Ramu <[email protected]>

Gives a sample to execute the little fs on external memory map (XiP) where the lfs1 partition is in internal mcu flash Signed-off-by: Francois Ramu <[email protected]>

FRASTM · 2024-02-20T08:29:52Z

The PR #68607 is now replacing this PR

FRASTM mentioned this pull request Aug 3, 2023

stm32h7 spi driver uses SRAM2 buffers in NOCACHE region #61021

Closed

FRASTM added platform: STM32 ST Micro STM32 DNM This PR should not be merged (Do Not Merge) area: QSPI Quad SPI labels Aug 3, 2023

FRASTM force-pushed the stm32h7_qspi_memmap branch 2 times, most recently from 855621a to 8fed638 Compare August 4, 2023 15:36

FRASTM mentioned this pull request Aug 7, 2023

stm32h7: qspi: Not accessible in memory mapped mode #59087

Closed

FRASTM force-pushed the stm32h7_qspi_memmap branch 4 times, most recently from f974b15 to d2614b1 Compare August 7, 2023 13:12

zephyrbot added manifest manifest-hal_stm32 labels Aug 7, 2023

FRASTM force-pushed the stm32h7_qspi_memmap branch 2 times, most recently from 7ba8369 to ff00d31 Compare August 11, 2023 14:35

GeorgeCGV reviewed Aug 15, 2023

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dts/arm/st/h7/stm32h7.dtsi Outdated Show resolved Hide resolved

FRASTM force-pushed the stm32h7_qspi_memmap branch from ff00d31 to 0943bae Compare September 6, 2023 09:34

FRASTM force-pushed the stm32h7_qspi_memmap branch 5 times, most recently from be66614 to 35e4044 Compare September 6, 2023 16:19

erwango requested changes Sep 7, 2023

View reviewed changes

zephyrbot removed manifest manifest-hal_stm32 DNM This PR should not be merged (Do Not Merge) labels Dec 12, 2023

FRASTM force-pushed the stm32h7_qspi_memmap branch 4 times, most recently from ea43dbd to 6ecb031 Compare January 29, 2024 15:58

FRASTM added 12 commits January 29, 2024 17:10

soc: arm: stm32u5 device with DCACHE for writing to NOR flash

5e10f8a

Enable the DCACHE1 in INCR burt mode to allow writing to the external NOR octoFlash when in MemoryMapped mode Signed-off-by: Francois Ramu <[email protected]>

boards: arm: stm32u585 disco kit for XiP on external octoflash

84aca6d

Define the Device tree of the b_u585i_iot02a disco kit to access the external NOR octo-flash in MemoryMapped mode for XiP Signed-off-by: Francois Ramu <[email protected]>

drivers: clock control of the stm32h7 skips pll1 re-init

8b6b9ab

Skip the PLL1 init if it is already running, this will avoid disabling the PLL when running after a jump from mcuboot Signed-off-by: Francois Ramu <[email protected]>

dts: arm: stm32h7 MPU attribute for the external Memory

1b1e047

Define the MPU attribute to be ATTR_MPU_IO for the qspi region, starting at 0x90000000 of the stm32h7 serie. Signed-off-by: Francois Ramu <[email protected]>

boards: arm: stm32h7b3 disco kit for XiP on external octoflash

d9a03a8

Define the Device tree of the stm32h7b3i_dk disco board to access the external NOR octo-flash in MemoryMapped mode for XiP Set openocd runner for debugging. Signed-off-by: Francois Ramu <[email protected]>

samples: subsys: fs_little fs on stm32h7b3 disco in xip

c54eca3

Gives a sample to execute the little fs on external memory map (XiP) where the lfs1 partition is in internal mcu flash Signed-off-by: Francois Ramu <[email protected]>

FRASTM force-pushed the stm32h7_qspi_memmap branch 5 times, most recently from 25675b2 to f2adc0b Compare February 1, 2024 15:56

FRASTM added 3 commits February 1, 2024 17:17

drivers: flash: stm32 qspi driver in Dual Flash Mode when MemoryMapped

c57cff6

Configure the quad-spi in DualFlash Mode when enabling the MemoryMapped then reading is possible with memcopy. Signed-off-by: Francois Ramu <[email protected]>

boards: arm: stm32 disco kit for XiP on external quadflash

279699a

Define the Device tree of the stm32l496g_disco board or stm32h750b disco kit to access the external NOR quad-flash in MemoryMapped mode for XiP Signed-off-by: Francois Ramu <[email protected]>

samples: subsys: fs_little fs on stm32 qspi disco in xip

fc6dd45

Gives a sample to execute the little fs on external memory map (XiP) where the lfs1 partition is in internal mcu flash Signed-off-by: Francois Ramu <[email protected]>

FRASTM force-pushed the stm32h7_qspi_memmap branch from f2adc0b to fc6dd45 Compare February 1, 2024 16:18

FRASTM closed this Feb 20, 2024

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drivers: stm32 qspi flash driver enables the MemoryMapped mode #61122

drivers: stm32 qspi flash driver enables the MemoryMapped mode #61122

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drivers: stm32 qspi flash driver enables the MemoryMapped mode #61122

drivers: stm32 qspi flash driver enables the MemoryMapped mode #61122

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