Fix writing clock wires

[lpawelcz]

This PR requires merging #658 first. After that, this PR will be rebased and turned to regular PR from draft.

This PR fixes FASM to Verilog conversion for designs that use clock inputs. Formerly fasm2bels script was skipping declaration of wire for the clock input that is used in clkpad module. This was causing problems when final verilog was simulated with testbench that contained line:

`default_nettype none

Now we add the declaration of clock wire as 'dummy wire' when the clkpad module is created.

This PR also enable for installed toolchain simulation tests of counter_gclk design that uses clock input.
Last change is to add simulation testbenches to ASSERT EXISTS tests.

[lpawelcz]

@tpagarani, @coolbreeze413 please have a look and review this one