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Fix writing clock wires #733

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Fix writing clock wires #733

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095ab6b
ql: pp3: utils: verilogmodule: write clock wires
lpawelcz Dec 16, 2021
82382c1
ql: cmake: add check for testbench files
lpawelcz Dec 16, 2021
51e4a88
ql: pp3: installed tests: counter_gclk: enable simulation
lpawelcz Dec 16, 2021
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5 changes: 3 additions & 2 deletions quicklogic/common/cmake/quicklogic_toolchain_test.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -98,13 +98,14 @@ function(ADD_BINARY_TOOLCHAIN_TEST)
list(APPEND ASSERT_EXISTS "${BUILD_DIR}/${FILE}")
endforeach()

string(REPLACE ";" "," ASSERT_EXISTS "${ASSERT_EXISTS}")

set(SIMULATION "")
if (${ADD_BINARY_TOOLCHAIN_TEST_ENABLE_SIMULATION})
set(SIMULATION ${TEST_NAME}_tb.v)
list(APPEND ASSERT_EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${SIMULATION}")
endif()

string(REPLACE ";" "," ASSERT_EXISTS "${ASSERT_EXISTS}")

# Add the test
set(TOOLCHAIN_COMMAND "${TOOLCHAIN_COMMAND} ${EXTRA_ARGS}")
add_test(NAME quicklogic_toolchain_test_${TEST_NAME}_${PINMAP}_${DEVICE}
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13 changes: 11 additions & 2 deletions quicklogic/pp3/tests/features/install_test/counter_gclk/CMakeLists.txt
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Original file line number Diff line number Diff line change
@@ -1,10 +1,13 @@
add_binary_toolchain_test(
TEST_NAME counter_gclk
ARCH pp3
DEVICE ql-eos-s3
PINMAP PD64
PCF chandalar.pcf
EXTRA_ARGS "-dump post_verilog"

ENABLE_SIMULATION

CHECK_CONSTRAINTS
ASSERT_USAGE PB-CLOCK=1,PB-GMUX=1,PB-BIDIR=4
ASSERT_TIMING fmax>56.0
Expand All @@ -18,13 +21,16 @@ add_binary_toolchain_test(
)

add_binary_toolchain_test(
TEST_NAME counter_gclk_wd30
TEST_NAME counter_gclk
SOURCES "counter_gclk.v"
ARCH pp3
DEVICE ql-pp3
PINMAP WD30
PCF jimbob4.pcf
EXTRA_ARGS "-dump post_verilog"

ENABLE_SIMULATION

CHECK_CONSTRAINTS
ASSERT_USAGE PB-CLOCK=1,PB-GMUX=1,PB-BIDIR=4
ASSERT_TIMING fmax>56.0
Expand All @@ -38,13 +44,16 @@ add_binary_toolchain_test(
)

add_binary_toolchain_test(
TEST_NAME counter_gclk_pd64
TEST_NAME counter_gclk
SOURCES "counter_gclk.v"
ARCH pp3
DEVICE ql-pp3
PINMAP PD64
PCF pd64.pcf
EXTRA_ARGS "-dump post_verilog"

ENABLE_SIMULATION

CHECK_CONSTRAINTS
ASSERT_USAGE PB-CLOCK=1,PB-GMUX=1,PB-BIDIR=4
ASSERT_TIMING fmax>40.0
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56 changes: 56 additions & 0 deletions quicklogic/pp3/tests/features/install_test/counter_gclk/counter_gclk_tb.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,56 @@
`timescale 1 ps / 1 ps

`default_nettype none

`define STRINGIFY(x) `"x`"


module tb;

task assert(input a);
begin
if (a==0) begin
$display("******************");
$display("* ASSERT FAILURE *");
$display("******************");
$dumpflush;
$finish_and_return(-1);
end
end
endtask

reg clk;
wire [3:0] out;
integer i;


`ifdef NO_SPLIT
top dut (
.clk (clk),
.led (out)
);
`else
top dut (
.\clk (clk),
.\led[0] (out[0]),
.\led[1] (out[1]),
.\led[2] (out[2]),
.\led[3] (out[3])
);
`endif

initial begin
clk = 1'b0;
`ifndef F2B
$sdf_annotate(`STRINGIFY(`SDF), dut);
`endif
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
for (i=1; i<64; i=i+1) begin
#1000000 clk = 1;
#500000 assert(out === (i % 16));
#500000 clk = 0;
end
#25 $finish();
end
endmodule
4 changes: 4 additions & 0 deletions quicklogic/pp3/utils/verilogmodule.py
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Original file line number Diff line number Diff line change
Expand Up @@ -283,6 +283,10 @@ def form_verilog_element(self, loc, typ: str, name: str, parameters: dict):
pin_map = self.qlal4s3_pinmap.get(moduletype, dict())

params.append(".{}({})".format(pin_map.get("IP", "IP"), ioname))
# Add clock wire
for inpname, inp in fixedparameters.items():
if inpname not in input_pins:
dummy_wires.append(f' wire {inp};')

result += f',\n{" " * len(result)}'.join(sorted(params)) + ');\n'
wires = ''
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