Update Yosys plugins package version

[mkurc-ant]

No description provided.

[tpagarani]

@mkurc-ant, CI is still failing

[mkurc-ant]

@tpagarani I'm still working on solving the failures one by one.

[mkurc-ant]

@tpagarani I have found and fixed a bug for the repacker script for qlf_k4n8 and the failing test now passes. However, I've found some other issues related both to Yosys and the architecture update:

The VPR architecture now supports DFFS, DFFNS, DFFSR, DFFNSR for CLB but not for IO tiles. However, even though neither set nor reset inputs are used Yosys seems to always emit DFFSR (for posedge clock) with both R and S connected to 1'b1. This makes VPR unable to pack them in IO tiles. That is why for example the test io_reg_max fails now.

I suggest re-visiting the synthesis flow so that Yosys emits FFs of the type actually needed by a design, not always DFFSR.

[tpagarani]

@mkurc-ant the reason all the ffs are being mapped to dffsr is that we are connecting control signals (set/reset/enable) to either 0 or 1. if we do not tie the control signals to known value and instead leave them floating then VPR packs the ffs which have different control signal value (e.g. a 'dff' and 'dffr') together leading to wrong functionality. Is there any other way to specify VPR not to pack such ffs together.

[mkurc-ant]

@tpagarani I understand. One way to achieve this is to have separate modes for whole CLBs instead of per flip-flop. Then once packer chooses one of them it won't be able to pack FFs of different types there. The similar thing would need to be done for IOs.

Another problem with having eg DFF (no S and R) in an operating mode is that there are no nets for those pins. So after repacking to the physical mode S and R of the physical flip-flop will be left unconnected.