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Add some bsp driver for HC32F4A8. #10333

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00e2e1f
Add some bsp driver for HC32F4A8.
JamieTx May 28, 2025
112e8c0
Fixed a warning in drv_eth.c.
JamieTx May 28, 2025
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11 changes: 10 additions & 1 deletion bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,16 @@ extern "C" {
#ifndef DAC1_INIT_PARAMS
#define DAC1_INIT_PARAMS \
{ \
.name = "dac1", \
.name = "dac1", \
.vref = 3300, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
}
#endif /* DAC1_INIT_PARAMS */
#endif /* BSP_USING_DAC1 */
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46 changes: 46 additions & 0 deletions bsp/hc32/ev_hc32f448_lqfp80/settings/project.dni
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Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
[PlDriver]
MemConfigValue=$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd
[PlCacheRanges]
CustomRanges0=0 0 262144 1 2048
CustomRangesText0=Flash
CustomRanges1=0 50334720 1024 1 2048
CustomRangesText1=OTP
CustomRanges2=0 536838144 65536 0 2048
CustomRangesText2=SRAM
CustomRanges3=0 537853952 4096 0 2048
CustomRangesText3=SRAMB
CustomRanges4=0 1073741824 536870912 2 0
CustomRangesText4=Peripheral
CustomRanges5=0 1610612736 536870912 0 2048
CustomRangesText5=EXMC SRAM
CustomRanges6=0 2281701376 1024 2 1024
CustomRangesText6=EXMC SRAM_REG
CustomRanges7=0 2550136832 67108864 1 2048
CustomRangesText7=QSPI
CustomRanges8=0 2617245696 67108864 2 67108864
CustomRangesText8=QSPI_REG
CustomRanges9=0 3758096384 536870912 2 0
CustomRangesText9=Private peripheral
[Stack]
FillEnabled=0
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnLogOnly=1
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[Disassemble mode]
mode=0
[Breakpoints2]
Count=0
[Aliases]
Count=0
SuppressDialog=0
[Jet]
DisableInterrupts=0
LeaveRunning=0
MultiCoreRunAll=0
[ArmDriver]
EnableCache=0
21 changes: 21 additions & 0 deletions bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,27 @@
#define DAC1_CH2_PIN (GPIO_PIN_05)
#endif

#if defined(BSP_USING_DAC2)
#define DAC2_CH1_PORT (GPIO_PORT_A)
#define DAC2_CH1_PIN (GPIO_PIN_06)
#define DAC2_CH2_PORT (GPIO_PORT_A)
#define DAC2_CH2_PIN (GPIO_PIN_07)
#endif

#if defined(BSP_USING_DAC3)
#define DAC3_CH1_PORT (GPIO_PORT_C)
#define DAC3_CH1_PIN (GPIO_PIN_04)
#define DAC3_CH2_PORT (GPIO_PORT_C)
#define DAC3_CH2_PIN (GPIO_PIN_05)
#endif

#if defined(BSP_USING_DAC4)
#define DAC4_CH1_PORT (GPIO_PORT_E)
#define DAC4_CH1_PIN (GPIO_PIN_07)
#define DAC4_CH2_PORT (GPIO_PORT_E)
#define DAC4_CH2_PIN (GPIO_PIN_08)
#endif

/*********** CAN configure *********/
#if defined(BSP_USING_CAN1)
#define CAN1_TX_PORT (GPIO_PORT_D)
Expand Down
48 changes: 44 additions & 4 deletions bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h
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Expand Up @@ -22,7 +22,17 @@ extern "C" {
#ifndef DAC1_INIT_PARAMS
#define DAC1_INIT_PARAMS \
{ \
.name = "dac1", \
.name = "dac1", \
.vref = 3300, \
.data_align = DAC_DATA_ALIGN_RIGHT, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
.ch1_amp_gain = DAC_AMP_GAIN_1, \
.ch2_amp_gain = DAC_AMP_GAIN_1, \
}
#endif /* DAC1_INIT_PARAMS */
#endif /* BSP_USING_DAC1 */
Expand All @@ -31,7 +41,17 @@ extern "C" {
#ifndef DAC2_INIT_PARAMS
#define DAC2_INIT_PARAMS \
{ \
.name = "dac2", \
.name = "dac2", \
.vref = 3300, \
.data_align = DAC_DATA_ALIGN_RIGHT, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
.ch1_amp_gain = DAC_AMP_GAIN_1, \
.ch2_amp_gain = DAC_AMP_GAIN_1, \
}
#endif /* DAC2_INIT_PARAMS */
#endif /* BSP_USING_DAC2 */
Expand All @@ -40,7 +60,17 @@ extern "C" {
#ifndef DAC3_INIT_PARAMS
#define DAC3_INIT_PARAMS \
{ \
.name = "dac3", \
.name = "dac3", \
.vref = 3300, \
.data_align = DAC_DATA_ALIGN_RIGHT, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
.ch1_amp_gain = DAC_AMP_GAIN_1, \
.ch2_amp_gain = DAC_AMP_GAIN_1, \
}
#endif /* DAC3_INIT_PARAMS */
#endif /* BSP_USING_DAC3 */
Expand All @@ -49,7 +79,17 @@ extern "C" {
#ifndef DAC4_INIT_PARAMS
#define DAC4_INIT_PARAMS \
{ \
.name = "dac4", \
.name = "dac4", \
.vref = 3300, \
.data_align = DAC_DATA_ALIGN_RIGHT, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
.ch1_amp_gain = DAC_AMP_GAIN_1, \
.ch2_amp_gain = DAC_AMP_GAIN_1, \
}
#endif /* DAC4_INIT_PARAMS */
#endif /* BSP_USING_DAC4 */
Expand Down
7 changes: 7 additions & 0 deletions bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c
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Expand Up @@ -105,6 +105,13 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
#endif

#if defined(RT_USING_DAC)
#if defined(BSP_USING_DAC2)
void EthPhyDisable(void)
{
TCA9539_WritePin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_PIN_RESET);
TCA9539_ConfigPin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_DIR_OUT);
}
#endif
rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
{
rt_err_t result = RT_EOK;
Expand Down
24 changes: 22 additions & 2 deletions bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,17 @@ extern "C" {
#ifndef DAC1_INIT_PARAMS
#define DAC1_INIT_PARAMS \
{ \
.name = "dac1", \
.name = "dac1", \
.vref = 3300, \
.data_align = DAC_DATA_ALIGN_RIGHT, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
}
#endif /* DAC1_INIT_PARAMS */
#endif /* BSP_USING_DAC1 */
Expand All @@ -30,7 +40,17 @@ extern "C" {
#ifndef DAC2_INIT_PARAMS
#define DAC2_INIT_PARAMS \
{ \
.name = "dac2", \
.name = "dac2", \
.vref = 3300, \
.data_align = DAC_DATA_ALIGN_RIGHT, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
}
#endif /* DAC2_INIT_PARAMS */
#endif /* BSP_USING_DAC2 */
Expand Down
10 changes: 9 additions & 1 deletion bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -61,5 +61,13 @@
/**
* @}
*/

/**
* @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition
* @{
*/
#define ETH_RST_PORT (TCA9539_IO_PORT1)
#define ETH_RST_PIN (EIO_ETH_RST)
/**
* @}
*/
#endif
17 changes: 9 additions & 8 deletions bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c
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Expand Up @@ -19,6 +19,7 @@
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)

#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
#define XTAL32_FCM_UNIT (CM_FCM1)

/**
* @brief This thread is used to monitor whether XTAL32 is stable.
Expand All @@ -42,22 +43,22 @@ void xtal32_fcm_thread_entry(void *parameter)
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
(void)FCM_Init(&stcFcmInit);
(void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit);
/* Enable FCM, to ensure xtal32 stable */
FCM_Cmd(ENABLE);
FCM_Cmd(XTAL32_FCM_UNIT, ENABLE);

while (1)
{
if (SET == FCM_GetStatus(FCM_FLAG_END))
if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END))
{
FCM_ClearStatus(FCM_FLAG_END);
if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END);
if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF)))
{
FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF);
}
else
{
(void)FCM_DeInit();
(void)FCM_DeInit(XTAL32_FCM_UNIT);
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
/* XTAL32 stabled */
break;
Expand All @@ -66,7 +67,7 @@ void xtal32_fcm_thread_entry(void *parameter)
u32TimeOut++;
if (u32TimeOut > u32Time)
{
(void)FCM_DeInit();
(void)FCM_DeInit(XTAL32_FCM_UNIT);
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
break;
Expand Down
40 changes: 28 additions & 12 deletions bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig
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Expand Up @@ -53,16 +53,6 @@ menu "Onboard Peripheral Drivers"
config ETH_INTERFACE_USING_RMII
bool "ETH Communication USING RMII"
endchoice

menuconfig ETH_PHY_USING_INTERRUPT_MODE
bool "Enable ETH PHY interrupt mode"
default n
if ETH_PHY_USING_INTERRUPT_MODE
config ETH_PHY_INTERRUPT_PIN
int "ETH PHY Interrupt pin number"
range 1 176
default 16
endif
endif

config BSP_USING_EXMC
Expand Down Expand Up @@ -142,6 +132,12 @@ menu "On-chip Peripheral Drivers"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0

config BSP_UART1_DMA_PING_BUFSIZE
int "Set UART1 RX DMA ping-pong buffer size"
range 32 65535
depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA
default 64
endif

menuconfig BSP_USING_UART2
Expand Down Expand Up @@ -169,6 +165,12 @@ menu "On-chip Peripheral Drivers"
range 0 65535
depends on RT_USING_SERIAL_V2
default 256

config BSP_UART2_DMA_PING_BUFSIZE
int "Set UART2 RX DMA ping-pong buffer size"
range 32 65535
depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA
default 64
endif

menuconfig BSP_USING_UART3
Expand Down Expand Up @@ -247,6 +249,12 @@ menu "On-chip Peripheral Drivers"
range 0 65535
depends on RT_USING_SERIAL_V2
default 256

config BSP_UART6_DMA_PING_BUFSIZE
int "Set UART6 RX DMA ping-pong buffer size"
range 32 65535
depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA
default 64
endif

menuconfig BSP_USING_UART7
Expand Down Expand Up @@ -274,8 +282,13 @@ menu "On-chip Peripheral Drivers"
range 0 65535
depends on RT_USING_SERIAL_V2
default 256
endif

config BSP_UART7_DMA_PING_BUFSIZE
int "Set UART7 RX DMA ping-pong buffer size"
range 32 65535
depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA
default 64
endif

menuconfig BSP_USING_UART8
bool "Enable UART8"
Expand Down Expand Up @@ -600,7 +613,7 @@ menu "On-chip Peripheral Drivers"
endif

menuconfig RT_USING_CAN_MCAN
bool "Enable CAN/MAN"
bool "Enable CAN/MCAN"
select RT_USING_CAN
select RT_CAN_USING_HDR
select BSP_USING_TCA9539
Expand Down Expand Up @@ -664,6 +677,9 @@ menu "On-chip Peripheral Drivers"

config BSP_RTC_USING_LRC
bool "RTC USING LRC"

config BSP_RTC_USING_XTAL_DIV
bool "RTC Using XTAL Division"
endchoice
endif

Expand Down
7 changes: 7 additions & 0 deletions bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c
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Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,13 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
#endif

#if defined(RT_USING_DAC)
#if defined(BSP_USING_DAC2)
void EthPhyDisable(void)
{
TCA9539_WritePin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_PIN_RESET);
TCA9539_ConfigPin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_DIR_OUT);
}
#endif
rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
{
rt_err_t result = RT_EOK;
Expand Down
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