This bug also occurred when using the Ubuntu 24.04 packaged version (yosys 0.33)

Reduced

module bad(
	input in,
	output reg [1:0] out
);
	assign out = {in, 1'b0};
endmodule

read_verilog bug.il; proc; aigmap; write_aiger -vmap /dev/null /dev/null

read_verilog bug.il; proc; aigmap; write_aiger -map /dev/null /dev/null

also crashes

Version
Yosys 0.50 (git sha1 b5170e1, g++ 11.4.0-1ubuntu1~22.04 -fPIC -O3)

On which OS did this happen?
Linux

Reproduction Steps
$ yosys -s syn.txt

syn.txt:
read_verilog -sv ../sources_1/new/*.sv
hierarchy -check -top Datapath
proc; opt; fsm; opt; memory; opt
techmap;
async2sync;
opt; flatten;
alumacc; dffunmap; aigmap; opt;

write_aiger -zinit -symbols -vmap datapath.aim datapath.aig
verilog is from: https://github.com/martinKindall/risc-v-single-cycle commit 5c6bf3c94553fdb00e7622c7ee5e6975fa5a38b4

Expected Behavior
Export and-inverter graph and mapping files, or report error.

Actual Behavior
terminate called after throwing an instance of 'std::out_of_range'
what(): dict::at()
Aborted (core dumped)

The issue mentioned above has been reproduced using Yosys version 0.50.

@zhaoxuying can you test with the PR #5109 which is linked on this issue as fixing the problem? If your case still fails on that PR then post a comment on the PR, not here. If you're just sharing this code to show that the issue still exists on Yosys 0.50 that is not helpful since there is a fix pending, and 0.53 is the latest not 0.50.

The latest version yosys 0.53 still exists the issue. I have post a comment on that PR #5109.