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std::out_of_range during write_aiger #5097

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nblei opened this issue May 6, 2025 · 3 comments · May be fixed by #5109
Open

std::out_of_range during write_aiger #5097

nblei opened this issue May 6, 2025 · 3 comments · May be fixed by #5109
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@nblei
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nblei commented May 6, 2025 •
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Version

Yosys 0.44 (git sha1 80ba43d, g++ 14.2.0-4ubuntu2~24.04 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

$ yosys -s syn.txt

syn.txt

read_verilog -sv ../sources_1/new/*.sv
hierarchy -check -top Datapath
proc; opt; fsm; opt; memory; opt
techmap;
async2sync;
opt; flatten;
alumacc; dffunmap; aigmap; opt;

write_aiger -zinit -symbols -vmap datapath.aim datapath.aig

verilog is from: https://github.com/martinKindall/risc-v-single-cycle commit 5c6bf3c94553fdb00e7622c7ee5e6975fa5a38b4

git clone --depth 1 https://github.com/martinKindall/risc-v-single-cycle commit temp_dir
cd temp_dir
git fetch --depth 1 origin 5c6bf3c94553fdb00e7622c7ee5e6975fa5a38b4
git checkout 5c6bf3c94553fdb00e7622c7ee5e6975fa5a38b4
mkdir syn
cd syn
echo "read_verilog -sv ../sources_1/new/*.sv \
                                                    hierarchy -check -top Datapath \
                                                    proc; opt; fsm; opt; memory; opt \
                                                    techmap; \
                                                    async2sync; \
                                                    opt; flatten; \
                                                    alumacc; dffunmap; aigmap; opt;\ 
                                                    write_aiger -zinit -symbols -vmap datapath.aim datapath.aig \
                                                    " > syn.txt
yosys -s syn.txt

Expected Behavior

Export and-inverter graph and mapping files, or report error.

Actual Behavior

uncaught std::out_of_range exception.
@nblei nblei added the pending-verification This issue is pending verification and/or reproduction label May 6, 2025
@nblei
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nblei commented May 6, 2025

This bug also occurred when using the Ubuntu 24.04 packaged version (yosys 0.33)

@widlarizer widlarizer added bug and removed pending-verification This issue is pending verification and/or reproduction labels May 7, 2025
@widlarizer
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Reduced

module bad(
	input in,
	output reg [1:0] out
);
	assign out = {in, 1'b0};
endmodule

read_verilog bug.il; proc; aigmap; write_aiger -vmap /dev/null /dev/null

@nblei
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nblei commented May 7, 2025

read_verilog bug.il; proc; aigmap; write_aiger -map /dev/null /dev/null

also crashes

@widlarizer widlarizer linked a pull request May 9, 2025 that will close this issue
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aiger: fix -map and -vmap YosysHQ/yosys
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@widlarizer @nblei