aiger: fix -map and -vmap

[widlarizer]

Fixes #5097

• add reduced reproducer as test
• make sure it actually fixes the bug on the originally reported reproducer

[widlarizer]

The basis for the correctness of this PR is that ordered_outputs is enumerated output_bits which holds unsigmapped output wire bits

[zhaoxuying]

Version

Yosys 0.53+70 (git sha1 3ef4c91, g++ 11.4.0-1ubuntu1~22.04 -fPIC -O3)

On which OS did this happen?
Linux

Reproduction Steps
$ ./yosys -s syn.txt

syn.txt:
read_verilog -sv ../sources_1/new/*.sv
hierarchy -check -top Datapath
proc; opt; fsm; opt; memory; opt
techmap;
async2sync;
opt; flatten;
alumacc; dffunmap; aigmap; opt;

write_aiger -zinit -symbols -vmap datapath.aim datapath.aig
verilog is from: https://github.com/martinKindall/risc-v-single-cycle commit 5c6bf3c94553fdb00e7622c7ee5e6975fa5a38b4

Expected Behavior
Export and-inverter graph and mapping files, or report error.

Actual Behavior

32. Executing AIGER backend.
    terminate called after throwing an instance of 'std::out_of_range'
    what(): dict::at()
    Aborted (core dumped)

The issue #5097 mentioned has been reproduced using the latest Yosys version 0.53.

[KrystalDelusion]

@zhaoxuying the version you used is from main, not this PR. As I said on the issue, if you test with the code from the PR and still get the error then you should make a comment. You have not done that, this PR has not been merged into main yet.

Yosys 0.53+70 (git sha1 3ef4c91, g++ 11.4.0-1ubuntu1~22.04 -fPIC -O3)

[zhaoxuying]

The PR is correct.