projects/ad9467_fmc: Add support on ZCU102

projects/ad9467_fmc/zcu102/Makefile

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+####################################################################################
+## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad9467_fmc_zcu102
+
+M_DEPS += ../common/ad9467_spi.v
+M_DEPS += ../common/ad9467_bd.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
+M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+
+LIB_DEPS += axi_ad9467
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_hdmi_tx
+LIB_DEPS += axi_i2s_adi
+LIB_DEPS += axi_spdif_tx
+LIB_DEPS += axi_sysid
+LIB_DEPS += sysid_rom
+LIB_DEPS += util_i2c_mixer
+
+include ../../scripts/project-xilinx.mk

projects/ad9467_fmc/zcu102/README.md

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+# AD9467-FMC/ZCU102 HDL Project
+
+## Building the project
+
+```
+cd projects/ad9467_fmc/ZCU102
+make
+```
+

projects/ad9467_fmc/zcu102/system_bd.tcl

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+###############################################################################
+## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
+source ../common/ad9467_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file

projects/ad9467_fmc/zcu102/system_constr.xdc

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+###############################################################################
+## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# ad9467
+
+set_property -dict {PACKAGE_PIN AA7     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_clk_in_p]         ; ## FMC_HPC0_CLK0_M2C_P
+set_property -dict {PACKAGE_PIN AA6     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_clk_in_n]         ; ## FMC_HPC0_CLK0_M2C_N
+set_property -dict {PACKAGE_PIN V4      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_or_p]        ; ## FMC_HPC0_LA08_P    
+set_property -dict {PACKAGE_PIN V3      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_or_n]        ; ## FMC_HPC0_LA08_N    
+set_property -dict {PACKAGE_PIN Y3      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_n[0]]     ; ## FMC_HPC0_LA00_CC_N 
+set_property -dict {PACKAGE_PIN Y4      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_p[0]]     ; ## FMC_HPC0_LA00_CC_P 
+set_property -dict {PACKAGE_PIN AB4     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_p[1]]     ; ## FMC_HPC0_LA01_CC_P 
+set_property -dict {PACKAGE_PIN AC4     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_n[1]]     ; ## FMC_HPC0_LA01_CC_N 
+set_property -dict {PACKAGE_PIN V2      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_p[2]]     ; ## FMC_HPC0_LA02_P    
+set_property -dict {PACKAGE_PIN V1      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_n[2]]     ; ## FMC_HPC0_LA02_N    
+set_property -dict {PACKAGE_PIN Y2      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_p[3]]     ; ## FMC_HPC0_LA03_P    
+set_property -dict {PACKAGE_PIN Y1      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_n[3]]     ; ## FMC_HPC0_LA03_N    
+set_property -dict {PACKAGE_PIN AA2     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_p[4]]     ; ## FMC_HPC0_LA04_P    
+set_property -dict {PACKAGE_PIN AA1     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_n[4]]     ; ## FMC_HPC0_LA04_N    
+set_property -dict {PACKAGE_PIN AB3     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_p[5]]     ; ## FMC_HPC0_LA05_P    
+set_property -dict {PACKAGE_PIN AC3     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_n[5]]     ; ## FMC_HPC0_LA05_N    
+set_property -dict {PACKAGE_PIN AC2     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_p[6]]     ; ## FMC_HPC0_LA06_P    
+set_property -dict {PACKAGE_PIN AC1     IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_n[6]]     ; ## FMC_HPC0_LA06_N    
+set_property -dict {PACKAGE_PIN U5      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_p[7]]     ; ## FMC_HPC0_LA07_P    
+set_property -dict {PACKAGE_PIN U4      IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports adc_data_in_n[7]]     ; ## FMC_HPC0_LA07_N    
+
+## spi
+
+set_property -dict {PACKAGE_PIN V11     IOSTANDARD LVCMOS18} [get_ports spi_csn_adc]                        ; ## FMC_HPC0_LA33_N
+set_property -dict {PACKAGE_PIN V12     IOSTANDARD LVCMOS18} [get_ports spi_csn_clk]                        ; ## FMC_HPC0_LA33_P
+set_property -dict {PACKAGE_PIN T11     IOSTANDARD LVCMOS18} [get_ports spi_clk]                            ; ## FMC_HPC0_LA32_N
+set_property -dict {PACKAGE_PIN U11     IOSTANDARD LVCMOS18} [get_ports spi_sdio]                           ; ## FMC_HPC0_LA32_P
+
+# clocks
+create_clock -name adc_clk      -period 4.00 [get_ports adc_clk_in_p]
+
+
+
+
+
+
+
+
+

projects/ad9467_fmc/zcu102/system_project.tcl

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+###############################################################################
+## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# load script
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project ad9467_fmc_zcu102
+adi_project_files ad9467_fmc_zcu102 [list \
+  "../common/ad9467_spi.v" \
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "system_top.v" \
+  "system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc"]
+
+adi_project_run ad9467_fmc_zcu102
+

projects/ad9467_fmc/zcu102/system_top.v

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  input   [12:0]  gpio_bd_i,
+  output  [ 7:0]  gpio_bd_o,
+
+  input                   adc_clk_in_n,
+  input                   adc_clk_in_p,
+  input       [ 7:0]      adc_data_in_n,
+  input       [ 7:0]      adc_data_in_p,
+  input                   adc_data_or_n,
+  input                   adc_data_or_p,
+  output                  spi_clk,
+  output                  spi_csn_adc,
+  output                  spi_csn_clk,
+  inout                   spi_sdio
+);
+
+  // internal signals
+  wire    [94:0]  gpio_i;
+  wire    [94:0]  gpio_o;
+
+  assign gpio_bd_o = gpio_o[7:0];
+
+  assign gpio_i[94:21] = gpio_o[94:21];
+  assign gpio_i[20: 8] = gpio_bd_i;
+  assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
+
+  wire   [ 1:0]   spi_csn;
+  wire            spi_miso;
+  wire            spi_mosi;
+
+  assign spi_csn_adc = spi_csn[0];
+  assign spi_csn_clk = spi_csn[1];
+
+  // instantiations
+
+  ad9467_spi i_spi (
+    .spi_csn(spi_csn),
+    .spi_clk(spi_clk),
+    .spi_mosi(spi_mosi),
+    .spi_miso(spi_miso),
+    .spi_sdio(spi_sdio));
+
+  system_wrapper i_system_wrapper (
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (),
+
+    .adc_clk_in_n(adc_clk_in_n),
+    .adc_clk_in_p(adc_clk_in_p),
+    .adc_data_in_n(adc_data_in_n),
+    .adc_data_in_p(adc_data_in_p),
+    .adc_data_or_n(adc_data_or_n),
+    .adc_data_or_p(adc_data_or_p),
+
+    .spi0_csn (spi_csn),
+    .spi0_miso (spi_miso),
+    .spi0_mosi (spi_mosi),
+    .spi0_sclk (spi_clk),
+    .spi1_csn (1'b1),
+    .spi1_miso (1'b0),
+    .spi1_mosi (),
+    .spi1_sclk ());
+
+endmodule