GitHub - jaimaSad23/Verilog_Assignment_CSE332L: In CSE332L: Computer Organization and Architecture Lab, I completed an assignment involving several Verilog tasks, where I solved the problems using behavioral, dataflow, and gate-level modeling.

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALU_16bit_output.png		ALU_16bit_output.png
Assignment-1(CSE332).docx		Assignment-1(CSE332).docx
Universal_Shift_Resister_output.png		Universal_Shift_Resister_output.png
Universal_shift_register_main.v		Universal_shift_register_main.v
UpDown_Counter_main.v		UpDown_Counter_main.v
UpDown_counter_testbench.v		UpDown_counter_testbench.v
Updown_counter_output1.png		Updown_counter_output1.png
alu_16bit_main.v		alu_16bit_main.v
alu_16bit_testbench.v		alu_16bit_testbench.v
full_adder_1bit_using_nand_nor_main.v		full_adder_1bit_using_nand_nor_main.v
full_adder_1bit_using_nand_nor_output.png		full_adder_1bit_using_nand_nor_output.png
full_adder_1bit_using_nand_nor_testbench.v		full_adder_1bit_using_nand_nor_testbench.v
ripple_carry_adder_8bit_main.v		ripple_carry_adder_8bit_main.v
ripple_carry_adder_8bit_testbench.v		ripple_carry_adder_8bit_testbench.v
ripple_carry_output.png		ripple_carry_output.png
universal_shift_register_testbench.v		universal_shift_register_testbench.v
waves output.pdf		waves output.pdf

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In CSE332L: Computer Organization and Architecture Lab, I completed an assignment involving several Verilog tasks, where I solved the problems using behavioral, dataflow, and gate-level modeling.