[LLHD] Preserve explicit register initializers through Deseq - #11081
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[LLHD] Preserve explicit register initializers through Deseq#110815iri wants to merge 2 commits into
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Carry explicit declaration initializers from MooreToCore to register presets in Deseq. This prevents BMC from treating initialized registers as having an unconstrained initial state without turning synthesized default zeros into register presets. Assisted-by: Codex:gpt-6
Assisted-by: Codex:gpt-6
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This preserves explicit SystemVerilog register initializers when lowering LLHD processes to
seq.firreg.Before this change, the initializer reached
llhd.sig, but was dropped when Deseq created the register. This left the initial BMC state unconstrained and could produce false counterexamples for initialized registers.For example:
The resulting register now has
preset 0, so BMC startscountat zero.MooreToCore marks explicit declaration initializers so Deseq can distinguish them from the zero values synthesized for variables without an initializer. Only explicit constant initializers become register presets.
Adds regression coverage for zero and nonzero initializers, and for registers that must remain unconstrained.
Tested with
check-circtand the initializer integration test.Assisted-by: Codex:gpt-6