[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs #132704
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Thanks for working on this! Can you please share a document that shows the instruction latencies? |
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| // LSU pipelines | ||
| // ============= | ||
| def : InstRW<[I6400WriteLSUStore], (instrs SB, SD, SH, SW, SDC1, SDC164, SWC1, SWC2_R6, |
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Is it possible avoid using SchedWriteRes + InstRW and using the normal SchedWrite + WriteRes instead?
InstRW really should be used for "ad-hoc fixing" nowadays (e.g. instruction A & B share the same scheduling class in their instruction definitions, but they should be in two different scheduling classes in your core)
Hi, please find the instruction latency at public document: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf |
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| mul $3, $2, $3 | ||
| sw $3, 8($sp) | ||
| div $2, $1 | ||
| sw $2, 0($sp) |
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Could you add more tests on simple integer and floating point arithmetics instructions, as well as some vector instructions (they're called MSA?).
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yes. I will add. thank you for the review
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I have extended the existing test to cover more instructions.
Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit
i6400 and i6500 are in-order cores. hence set BufferSize and MicroBufferSize to 0
- remove hasNoSchedulingInfo in Mips32r6InstrInfo.td - define BufferSize to 0 for all resources - remove timeline test in llvm-mca testcase
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Extend i64..s to cover more instructions including MSA
Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor.
i6400 and i6500 share same instruction latencies.
CPU has following pipelines
Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf