[CodeGen][NPM] VirtRegRewriter: Set VirtReg flag

[optimisan]

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[optimisan]

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• [CodeGen][NPM] Account inserted passes for -start/stop options #138830
• [CodeGen][NPM] Port ProcessImplicitDefs to NPM #138829
• [CodeGen][NPM] Register Function Passes #138828
• [CodeGen][NPM] Read TargetMachine's EnableIPRA option #138670
• [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag #138660 👈 (View in Graphite)
• [CodeGen][NPM] Port PostRAMachineSinking to NPM #138497
• [AMDGPU][NPM] Register AMDGPUWaitSGPRHazards pass #138496
• [CodeGen][NPM] Port InitUndef to NPM #138495
• [AMDGPU][NPM] Complete optimized regalloc pipeline #138491
• [CodeGen][NPM] Support CodeGenSCCOrder in pipeline #136818
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[llvmbot]

@llvm/pr-subscribers-llvm-regalloc

Author: Akshat Oke (optimisan)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/138660.diff

2 Files Affected:

• (modified) llvm/include/llvm/CodeGen/VirtRegMap.h (+8)
• (modified) llvm/lib/CodeGen/VirtRegMap.cpp (+2)

diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h
index f5fba0d65401e..37d382650ac1f 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -248,6 +248,14 @@ class VirtRegRewriterPass : public PassInfoMixin<VirtRegRewriterPass> {
   static bool isRequired() { return true; }
 
   void printPipeline(raw_ostream &OS, function_ref<StringRef(StringRef)>) const;
+
+  MachineFunctionProperties getSetProperties() const {
+    if (ClearVirtRegs) {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::NoVRegs);
+    }
+    return {};
+  }
 };
 
 } // end llvm namespace
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 49e819e2d10f7..839905d5e3860 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -302,6 +302,8 @@ bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {
 PreservedAnalyses
 VirtRegRewriterPass::run(MachineFunction &MF,
                          MachineFunctionAnalysisManager &MFAM) {
+  MFPropsModifier _(*this, MF);
+
   VirtRegMap &VRM = MFAM.getResult<VirtRegMapAnalysis>(MF);
   LiveIntervals &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
   LiveRegMatrix &LRM = MFAM.getResult<LiveRegMatrixAnalysis>(MF);