Skip to content
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 7 additions & 0 deletions sw/device/tests/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -3903,6 +3903,7 @@ opentitan_test(
"//hw/top_earlgrey:sim_verilator": None,
"//hw/top_earlgrey:fpga_cw340_sival": None,
"//hw/top_earlgrey:fpga_cw340_sival_rom_ext": None,
"//hw/top_earlgrey:sim_qemu_rom_with_fake_keys": None,
},
),
fpga = fpga_params(
Expand All @@ -3914,6 +3915,12 @@ opentitan_test(
""",
test_harness = "//sw/host/tests/chip/spi_device:spi_device_tpm_test",
),
qemu = qemu_params(
test_cmd = """
"{firmware:elf}"
""",
test_harness = "//sw/host/tests/chip/spi_device:spi_device_tpm_test",
),
silicon = silicon_params(
test_cmd = """
--bootstrap="{firmware}"
Expand Down
3 changes: 3 additions & 0 deletions sw/host/opentitanlib/src/app/config/opentitan_qemu.json
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,9 @@
}
]
},
{
"name": "SPI_TPM"
}
],
"uarts": [
{
Expand Down
1 change: 1 addition & 0 deletions sw/host/opentitanlib/src/tpm/driver.rs
Original file line number Diff line number Diff line change
Expand Up @@ -277,6 +277,7 @@ impl SpiDriver {
if Instant::now().duration_since(start_time) > TIMEOUT {
bail!(TpmError::Timeout)
}
thread::sleep(Duration::from_millis(1));
}
}
Ok(())
Expand Down
11 changes: 9 additions & 2 deletions sw/host/opentitanlib/src/transport/qemu/spi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,9 @@ use anyhow::{Context, ensure};
use serialport::TTYPort;

use crate::io::gpio;
use crate::io::spi::{AssertChipSelect, MaxSizes, Target, Transfer, TransferMode};
use crate::io::spi::{
AssertChipSelect, MaxSizes, Target, TargetChipDeassert, Transfer, TransferMode,
};
use crate::transport::TransportError;
use crate::util::voltage::Voltage;

Expand Down Expand Up @@ -205,7 +207,8 @@ impl Target for QemuSpi {
fn assert_cs(self: Rc<Self>) -> anyhow::Result<AssertChipSelect> {
// Could potentially be implemented by sending an empty packet that
// holds the CS and another which deasserts when dropped.
Err(TransportError::UnsupportedOperation.into())
log::warn!("TODO: Implement CS for Qemu");
Ok(AssertChipSelect::new(self))
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Does this change make sense? It will allow host code that calls spi.assert_cs() to compile, but this isn't actually sending packets with the CS signals to QEMU.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

In my interpretation, CS doesn't make sense for QEMU because it's now a bus implemented with pins, so I think that the qemu transport should just fake it.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I added a warning for now. As we disscussed, this would need a larger refactor of the way the ChipSelect is handled.

}

fn set_voltage(&self, _voltage: Voltage) -> anyhow::Result<()> {
Expand All @@ -216,3 +219,7 @@ impl Target for QemuSpi {
Err(TransportError::UnsupportedOperation.into())
}
}

impl TargetChipDeassert for QemuSpi {
fn deassert_cs(&self) {}
}
Loading