Fix Kill_S signal #153
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Fix Kill_S signal #153
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| logic hold_en; | ||
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| logic Kill_SI_pulp = (flush_i === 1'b1) || (reg_ena_i[NUM_INP_REGS-1] === 1'b1); //Guarded against X | ||
| `ifndef SYNTHESIS |
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I would recommend the industry-standard //synopsys translate_on and //synopsys translate_off pragmas. Virtually all commercial synthesis tools recognise these and it avoids using yet-another Verilog macro.
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This blocks propergating value X to Kill_SI in div_sqrt_top_mvp.
Related to issue #152