Add early_valid signal to check for structural hazards

[ricted98]

In CVA6, the FPU shares a writeback port with the secondary ALU used in superscalar mode. Until now, FPU support was disabled to prevent structural hazards. To enable FPU support in superscalar mode, an additional signal is required to indicate when the FPU will produce a valid result in the next cycle.
This occurs in two cases:

• A valid result is currently in the penultimate pipeline stage.
• A valid result is in the final pipeline stage, but the ready signal was not asserted in the current cycle.

[ricted98]

Hi @MikeOpenHWGroup, I am pinging you as I am not sure who should review this PR, as #151 suggests the current code owner is no longer involved. Thanks!

[MikeOpenHWGroup]

You are right @ricted98, currently this project lacks a code owner, although @IhsaneTahir is doing a great job of finding bugs! 🤣 I am actively recruiting one (or ideally more) people to help with this.

[rgiunti]

Hi @ricted98, I tested your PR using the UVM testbench https://github.com/openhwgroup/cvfpu-uvm with CVA6 updated to your PR #3085. As a regression test I ran 10000 random transactions with random operation, operands, FP format and FP rounding mode repeated for 10 different seeds. In this UVM testbench the results have been compared with those given by the MPFR golden model. The test passed and so the PR can be merged in my opinion.

[MikeOpenHWGroup]

Thanks @ricted98 and @rgiunti. I am approving and merging based on @rgiunti's successful testing,