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Merged
merged 3 commits into from
Oct 21, 2025
Merged

Add early_valid signal to check for structural hazards #156

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fc2f8a2
src: add `early_valid` signal
ricted98 Sep 5, 2024
1ff6b1b
docs: update README
ricted98 Aug 28, 2025
5bc808b
Merge branch 'openhwgroup:develop' into rt/early-valid
ricted98 Oct 9, 2025
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3 changes: 2 additions & 1 deletion README.md
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Expand Up @@ -110,7 +110,8 @@ fpnew_top #(
.tag_o,
.out_valid_o,
.out_ready_i,
.busy_o
.busy_o,
.early_valid_o
);
```

Expand Down
1 change: 1 addition & 0 deletions docs/README.md
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Expand Up @@ -70,6 +70,7 @@ As the width of some input/output signals is defined by the configuration, it is
| `out_valid_o` | out | `logic` | Output data valid (see [Handshake](#handshake-interface)) |
| `out_ready_i` | in | `logic` | Output interface ready (see [Handshake](#handshake-interface)) |
| `busy_o` | out | `logic` | FPU operation in flight |
| `early_valid_o` | out | `logic` | Output data valid in the next cycle |

#### Data Types

Expand Down
19 changes: 18 additions & 1 deletion src/fpnew_cast_multi.sv
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Expand Up @@ -60,7 +60,9 @@ module fpnew_cast_multi #(
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
input logic [ExtRegEnaWidth-1:0] reg_ena_i,
// Early valid for external structural hazard generation
output logic early_out_valid_o
);

// ----------
Expand Down Expand Up @@ -803,4 +805,19 @@ module fpnew_cast_multi #(
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q});

// Early valid_o signal. This is used for dispatching instructions for dual-issue processor.
if (NUM_OUT_REGS > 0) begin
assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS],
out_pipe_valid_q[NUM_OUT_REGS-1]};
end else if (NUM_MID_REGS > 0) begin
assign early_out_valid_o = |{mid_pipe_valid_q[NUM_MID_REGS] & ~mid_pipe_ready[NUM_OUT_REGS],
mid_pipe_valid_q[NUM_MID_REGS-1]};
end else if (NUM_INP_REGS > 0) begin
assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS],
inp_pipe_valid_q[NUM_INP_REGS-1]};
end else begin
assign early_out_valid_o = 1'b0;
end

endmodule
16 changes: 15 additions & 1 deletion src/fpnew_divsqrt_multi.sv
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Expand Up @@ -60,7 +60,9 @@ module fpnew_divsqrt_multi #(
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
input logic [ExtRegEnaWidth-1:0] reg_ena_i,
// Early valid for external structural hazard generation
output logic early_out_valid_o
);

// ----------
Expand Down Expand Up @@ -381,4 +383,16 @@ module fpnew_divsqrt_multi #(
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q});

// Early valid_o signal. This is used for dispatching instructions for dual-issue processor.
if (NUM_OUT_REGS > 0) begin
assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS],
out_pipe_valid_q[NUM_OUT_REGS-1]};
end else if (NUM_INP_REGS > 0) begin
assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS],
inp_pipe_valid_q[NUM_INP_REGS-1]};
end else begin
assign early_out_valid_o = 1'b0;
end

endmodule
15 changes: 14 additions & 1 deletion src/fpnew_divsqrt_th_32.sv
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Expand Up @@ -57,7 +57,9 @@ module fpnew_divsqrt_th_32 #(
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
input logic [ExtRegEnaWidth-1:0] reg_ena_i,
// Early valid for external structural hazard generation
output logic early_out_valid_o
);

// ----------
Expand Down Expand Up @@ -476,4 +478,15 @@ module fpnew_divsqrt_th_32 #(
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q});

// Early valid_o signal. This is used for dispatching instructions for dual-issue processor.
if (NUM_OUT_REGS > 0) begin
assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS],
out_pipe_valid_q[NUM_OUT_REGS-1]};
end else if (NUM_INP_REGS > 0) begin
assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS],
inp_pipe_valid_q[NUM_INP_REGS-1]};
end else begin
assign early_out_valid_o = 1'b0;
end
endmodule
15 changes: 14 additions & 1 deletion src/fpnew_divsqrt_th_64_multi.sv
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Expand Up @@ -62,7 +62,9 @@ module fpnew_divsqrt_th_64_multi #(
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
input logic [ExtRegEnaWidth-1:0] reg_ena_i,
// Early valid for external structural hazard generation
output logic early_out_valid_o
);

// ----------
Expand Down Expand Up @@ -496,5 +498,16 @@ module fpnew_divsqrt_th_64_multi #(
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q});

// Early valid_o signal. This is used for dispatching instructions for dual-issue processor.
if (NUM_OUT_REGS > 0) begin
assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS],
out_pipe_valid_q[NUM_OUT_REGS-1]};
end else if (NUM_INP_REGS > 0) begin
assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS],
inp_pipe_valid_q[NUM_INP_REGS-1]};
end else begin
assign early_out_valid_o = 1'b0;
end
endmodule

20 changes: 18 additions & 2 deletions src/fpnew_fma.sv
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Expand Up @@ -53,7 +53,9 @@ module fpnew_fma #(
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
input logic [ExtRegEnaWidth-1:0] reg_ena_i,
// Early valid for external structural hazard generation
output logic early_out_valid_o
);

// ----------
Expand Down Expand Up @@ -620,7 +622,7 @@ module fpnew_fma #(

// Classification after rounding
assign uf_after_round = (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) // denormal
|| ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) &&
|| ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) &&
((round_sticky_bits != 2'b11) || (!sum_sticky_bits[MAN_BITS*2 + 4] && ((rnd_mode_q == fpnew_pkg::RNE) || (rnd_mode_q == fpnew_pkg::RMM)))));
assign of_after_round = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // exponent all ones

Expand Down Expand Up @@ -698,4 +700,18 @@ module fpnew_fma #(
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q});

// Early valid_o signal. This is used for dispatching instructions for dual-issue processor.
if (NUM_OUT_REGS > 0) begin
assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS],
out_pipe_valid_q[NUM_OUT_REGS-1]};
end else if (NUM_MID_REGS > 0) begin
assign early_out_valid_o = |{mid_pipe_valid_q[NUM_MID_REGS] & ~mid_pipe_ready[NUM_OUT_REGS],
mid_pipe_valid_q[NUM_MID_REGS-1]};
end else if (NUM_INP_REGS > 0) begin
assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS],
inp_pipe_valid_q[NUM_INP_REGS-1]};
end else begin
assign early_out_valid_o = 1'b0;
end
endmodule
23 changes: 20 additions & 3 deletions src/fpnew_fma_multi.sv
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Expand Up @@ -57,7 +57,9 @@ module fpnew_fma_multi #(
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
input logic [ExtRegEnaWidth-1:0] reg_ena_i,
// Early valid for external structural hazard generation
output logic early_out_valid_o
);

// ----------
Expand Down Expand Up @@ -796,9 +798,9 @@ module fpnew_fma_multi #(

if (FpFmtConfig[fmt]) begin : active_format
always_comb begin : post_process
// detect of / uf
// detect of / uf
fmt_uf_after_round[fmt] = (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) // denormal
|| ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) &&
|| ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) &&
((round_sticky_bits != 2'b11) || (!sum_sticky_bits[MAN_BITS*2 + 4] && ((rnd_mode_q == fpnew_pkg::RNE) || (rnd_mode_q == fpnew_pkg::RMM)))));
fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp.

Expand Down Expand Up @@ -892,4 +894,19 @@ module fpnew_fma_multi #(
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q});

// Early valid_o signal. This is used for dispatching instructions for dual-issue processor.
if (NUM_OUT_REGS > 0) begin
assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS],
out_pipe_valid_q[NUM_OUT_REGS-1]};
end else if (NUM_MID_REGS > 0) begin
assign early_out_valid_o = |{mid_pipe_valid_q[NUM_MID_REGS] & ~mid_pipe_ready[NUM_OUT_REGS],
mid_pipe_valid_q[NUM_MID_REGS-1]};
end else if (NUM_INP_REGS > 0) begin
assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS],
inp_pipe_valid_q[NUM_INP_REGS-1]};
end else begin
assign early_out_valid_o = 1'b0;
end

endmodule
16 changes: 15 additions & 1 deletion src/fpnew_noncomp.sv
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Expand Up @@ -55,7 +55,9 @@ module fpnew_noncomp #(
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
input logic [ExtRegEnaWidth-1:0] reg_ena_i,
// Early valid for external structural hazard generation
output logic early_out_valid_o
);

// ----------
Expand Down Expand Up @@ -417,4 +419,16 @@ module fpnew_noncomp #(
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, out_pipe_valid_q});

// Early valid_o signal. This is used for dispatching instructions for dual-issue processor.
if (NUM_OUT_REGS > 0) begin
assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS],
out_pipe_valid_q[NUM_OUT_REGS-1]};
end else if (NUM_INP_REGS > 0) begin
assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS],
inp_pipe_valid_q[NUM_INP_REGS-1]};
end else begin
assign early_out_valid_o = 1'b0;
end

endmodule
59 changes: 33 additions & 26 deletions src/fpnew_opgroup_block.sv
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Expand Up @@ -59,7 +59,8 @@ module fpnew_opgroup_block #(
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o
output logic busy_o,
output logic early_valid_o
);

// ----------------
Expand All @@ -74,6 +75,7 @@ module fpnew_opgroup_block #(

// Handshake signals for the slices
logic [NUM_FORMATS-1:0] fmt_in_ready, fmt_out_valid, fmt_out_ready, fmt_busy;
logic [NUM_FORMATS-1:0] early_valid;
output_t [NUM_FORMATS-1:0] fmt_outputs;

// -----------
Expand Down Expand Up @@ -115,25 +117,26 @@ module fpnew_opgroup_block #(
) i_fmt_slice (
.clk_i,
.rst_ni,
.operands_i ( operands_i ),
.is_boxed_i ( is_boxed_i[fmt] ),
.operands_i ( operands_i ),
.is_boxed_i ( is_boxed_i[fmt] ),
.rnd_mode_i,
.op_i,
.op_mod_i,
.vectorial_op_i,
.tag_i,
.simd_mask_i ( mask_slice ),
.in_valid_i ( in_valid ),
.in_ready_o ( fmt_in_ready[fmt] ),
.simd_mask_i ( mask_slice ),
.in_valid_i ( in_valid ),
.in_ready_o ( fmt_in_ready[fmt] ),
.flush_i,
.result_o ( fmt_outputs[fmt].result ),
.status_o ( fmt_outputs[fmt].status ),
.extension_bit_o( fmt_outputs[fmt].ext_bit ),
.tag_o ( fmt_outputs[fmt].tag ),
.out_valid_o ( fmt_out_valid[fmt] ),
.out_ready_i ( fmt_out_ready[fmt] ),
.busy_o ( fmt_busy[fmt] ),
.reg_ena_i ( '0 )
.result_o ( fmt_outputs[fmt].result ),
.status_o ( fmt_outputs[fmt].status ),
.extension_bit_o ( fmt_outputs[fmt].ext_bit ),
.tag_o ( fmt_outputs[fmt].tag ),
.out_valid_o ( fmt_out_valid[fmt] ),
.out_ready_i ( fmt_out_ready[fmt] ),
.busy_o ( fmt_busy[fmt] ),
.reg_ena_i ( '0 ),
.early_out_valid_o( early_valid[fmt] )
);
// If the format wants to use merged ops, tie off the dangling ones not used here
end else if (FpFmtMask[fmt] && ANY_MERGED && !IS_FIRST_MERGED) begin : merged_unused
Expand All @@ -149,7 +152,7 @@ module fpnew_opgroup_block #(
assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE};
assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE;
assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE);

assign early_valid[fmt] = 1'b0;
// Tie off disabled formats
end else if (!FpFmtMask[fmt] || (FmtUnitTypes[fmt] == fpnew_pkg::DISABLED)) begin : disable_fmt
assign fmt_in_ready[fmt] = 1'b0; // don't accept operations
Expand All @@ -160,6 +163,7 @@ module fpnew_opgroup_block #(
assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE};
assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE;
assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE);
assign early_valid[fmt] = 1'b0;
end
end

Expand Down Expand Up @@ -198,18 +202,19 @@ module fpnew_opgroup_block #(
.int_fmt_i,
.vectorial_op_i,
.tag_i,
.simd_mask_i ( simd_mask_i ),
.in_valid_i ( in_valid ),
.in_ready_o ( fmt_in_ready[FMT] ),
.simd_mask_i ( simd_mask_i ),
.in_valid_i ( in_valid ),
.in_ready_o ( fmt_in_ready[FMT] ),
.flush_i,
.result_o ( fmt_outputs[FMT].result ),
.status_o ( fmt_outputs[FMT].status ),
.extension_bit_o ( fmt_outputs[FMT].ext_bit ),
.tag_o ( fmt_outputs[FMT].tag ),
.out_valid_o ( fmt_out_valid[FMT] ),
.out_ready_i ( fmt_out_ready[FMT] ),
.busy_o ( fmt_busy[FMT] ),
.reg_ena_i ( '0 )
.result_o ( fmt_outputs[FMT].result ),
.status_o ( fmt_outputs[FMT].status ),
.extension_bit_o ( fmt_outputs[FMT].ext_bit ),
.tag_o ( fmt_outputs[FMT].tag ),
.out_valid_o ( fmt_out_valid[FMT] ),
.out_ready_i ( fmt_out_ready[FMT] ),
.busy_o ( fmt_busy[FMT] ),
.reg_ena_i ( '0 ),
.early_out_valid_o( early_valid[FMT] )
);

end
Expand Down Expand Up @@ -244,6 +249,8 @@ module fpnew_opgroup_block #(
assign extension_bit_o = arbiter_output.ext_bit;
assign tag_o = arbiter_output.tag;

assign early_valid_o = |early_valid;

assign busy_o = (| fmt_busy);

endmodule
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