8350085: RISC-V: Enable upper GPR registers in C1

[Elain520]

This change enables the upper general-purpose registers for RISC-V C1 register allocation.

It extends the C1 caller-save register set from 13 to 21 registers, updates FrameMap and LinearScan register boundaries, and makes Runtime1 OopMap generation use the FrameMap caller-save register list. x9 remains reserved because it is used directly by C1 stubs.

Testing:

• RISC-V fastdebug hotspot build
• RISC-V fastdebug images build
• Six targeted C1 tests on A210 with -XX:TieredStopAtLevel=1

TestConcurrentPatching was stopped after exceeding the practical test window and is not counted as either a pass or a product failure.

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Progress

• Change must not contain extraneous whitespace
• Commit message must refer to an issue
• Change must be properly reviewed (2 reviews required, with at least 1 Reviewer, 1 Author)

Issue

• JDK-8350085: RISC-V: Enable upper GPR registers in C1 (Enhancement - P4)

Reviewing

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[openjdk]

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[mlbridge]

Webrevs

• 00: Full (97643ee2)

[RealFYang]

What about the performance impact? Any numbers to look at?