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8350085: RISC-V: Enable upper GPR registers in C1 #32496

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8350085: RISC-V: Enable upper GPR registers in C1 #32496

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8350085: RISC-V: Enable upper GPR registers in C1
Elain520 Aug 18, 2026
97643ee
Merge remote-tracking branch 'origin/master' into JDK-8350085-riscv-c…
Elain520 Aug 24, 2026
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4 changes: 2 additions & 2 deletions src/hotspot/cpu/riscv/c1_Defs_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -38,11 +38,11 @@ enum {
pd_nof_fpu_regs_frame_map = FloatRegister::number_of_registers, // number of float registers used during code emission

// caller saved
pd_nof_caller_save_cpu_regs_frame_map = 13, // number of registers killed by calls
pd_nof_caller_save_cpu_regs_frame_map = 21, // number of registers killed by calls
pd_nof_caller_save_fpu_regs_frame_map = 32, // number of float registers killed by calls

pd_first_callee_saved_reg = pd_nof_caller_save_cpu_regs_frame_map,
pd_last_callee_saved_reg = 21,
pd_last_callee_saved_reg = pd_first_callee_saved_reg - 1, // in fact, no callee saved regs

pd_last_allocatable_cpu_reg = pd_nof_caller_save_cpu_regs_frame_map - 1,

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19 changes: 14 additions & 5 deletions src/hotspot/cpu/riscv/c1_FrameMap_riscv.cpp
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Expand Up @@ -176,17 +176,20 @@ LIR_Opr FrameMap::_caller_save_fpu_regs[] = {};
// |---..---|
// |---f0---|
// |---x27--|
// |---x9---|
// |---x23--|
// |---x8---|
// |---x4---|
// |---x3---|
// |---x2---|
// |---x1---|
// |---x0---|
// |---x26--|<---pd_last_callee_saved_reg
// |---x26--|
// |---x25--|
// |---x24--|
// |---x22--|
// |---..---|
// |---x18--|
// |---x9---|<---pd_first_callee_saved_reg
// |---x31--|
// |---..---|
// |---x28--|
Expand Down Expand Up @@ -214,9 +217,6 @@ void FrameMap::initialize() {
map_register(i, x29); r29_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, x30); r30_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, x31); r31_opr = LIR_OprFact::single_cpu(i); i++;

// callee save register
map_register(i, x9); r9_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, x18); r18_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, x19); r19_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, x20); r20_opr = LIR_OprFact::single_cpu(i); i++;
Expand All @@ -234,6 +234,7 @@ void FrameMap::initialize() {
map_register(i, x4); r4_opr = LIR_OprFact::single_cpu(i); i++; // thread
map_register(i, x8); r8_opr = LIR_OprFact::single_cpu(i); i++; // fp
map_register(i, x23); r23_opr = LIR_OprFact::single_cpu(i); i++; // java thread
map_register(i, x9); r9_opr = LIR_OprFact::single_cpu(i); i++;
map_register(i, x27); r27_opr = LIR_OprFact::single_cpu(i); i++; // heapbase

// tmp register
Expand Down Expand Up @@ -265,6 +266,14 @@ void FrameMap::initialize() {
_caller_save_cpu_regs[i++] = r29_opr;
_caller_save_cpu_regs[i++] = r30_opr;
_caller_save_cpu_regs[i++] = r31_opr;
_caller_save_cpu_regs[i++] = r18_opr;
_caller_save_cpu_regs[i++] = r19_opr;
_caller_save_cpu_regs[i++] = r20_opr;
_caller_save_cpu_regs[i++] = r21_opr;
_caller_save_cpu_regs[i++] = r22_opr;
_caller_save_cpu_regs[i++] = r24_opr;
_caller_save_cpu_regs[i++] = r25_opr;
_caller_save_cpu_regs[i++] = r26_opr;

_init_done = true;

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6 changes: 3 additions & 3 deletions src/hotspot/cpu/riscv/c1_LinearScan_riscv.hpp
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Expand Up @@ -42,10 +42,10 @@ inline bool LinearScan::requires_adjacent_regs(BasicType type) {

inline bool LinearScan::is_caller_save(int assigned_reg) {
assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
if (assigned_reg < pd_first_callee_saved_reg) {
if (assigned_reg < FrameMap::nof_caller_save_cpu_regs()) {
return true;
}
if (assigned_reg > pd_last_callee_saved_reg && assigned_reg < pd_first_callee_saved_fpu_reg_1) {
if (assigned_reg >= pd_first_fpu_reg && assigned_reg < pd_first_callee_saved_fpu_reg_1) {
return true;
}
if (assigned_reg > pd_last_callee_saved_fpu_reg_1 && assigned_reg < pd_first_callee_saved_fpu_reg_2) {
Expand Down Expand Up @@ -74,7 +74,7 @@ inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur)
} else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT ||
cur->type() == T_ADDRESS || cur->type() == T_METADATA) {
_first_reg = pd_first_cpu_reg;
_last_reg = pd_last_allocatable_cpu_reg;
_last_reg = FrameMap::last_cpu_reg();
return true;
}
return false;
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10 changes: 2 additions & 8 deletions src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -262,14 +262,8 @@ static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers) {
OopMap* oop_map = new OopMap(frame_size_in_slots, 0);
assert_cond(oop_map != nullptr);

// caller save registers only, see FrameMap::initialize
// in c1_FrameMap_riscv.cpp for detail.
const static Register caller_save_cpu_regs[FrameMap::max_nof_caller_save_cpu_regs] = {
x7, x10, x11, x12, x13, x14, x15, x16, x17, x28, x29, x30, x31
};

for (int i = 0; i < FrameMap::max_nof_caller_save_cpu_regs; i++) {
Register r = caller_save_cpu_regs[i];
for (int i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
Register r = FrameMap::caller_save_cpu_reg_at(i)->as_register();
int sp_offset = cpu_reg_save_offsets[r->encoding()];
oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset),
r->as_VMReg());
Expand Down