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RFC: add testcase for new p extension - #648

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aswaterman merged 5 commits into
riscv-software-src:masterfrom
chihminchao:rvp
Jun 3, 2026
Merged

RFC: add testcase for new p extension#648
aswaterman merged 5 commits into
riscv-software-src:masterfrom
chihminchao:rvp

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The current version is not fully verified with spike implementation because there are some issues in toolchains I can get.

- Add rv64up/ and rv32up/ directories for P-extension tests
- Add Makefrag files for both directories
- Update main Makefile to include P-extension tests
- Add padd_b test as initial test case
- Use -march=rv64gp and -march=rv32gp for compilation
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
chihminchao force-pushed the rvp branch 2 times, most recently from ba5c992 to 4b323c2 Compare May 21, 2026 15:31
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Update: 2026/05/21

  1. squash commits to reduce rebase effort
  2. verification the implementation with latest spike (there are some fix which will be sent to riscv-isa-sim later)

To do

  1. add vxsat initialization and checking for instructions having saturation behavior.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
…slx, srx

Added tests:
- rv32up/rev.S: RV32 bit reverse (grevi shamt=31)
- rv64up/rev.S: RV64 bit reverse (grevi shamt=63)
- rv64up/rev16.S: RV64 16-bit group swap (grevi shamt=48)
- rv64up/mvm.S: RV64 move if mask
- rv64up/mvmn.S: RV64 move if not mask
- rv64up/merge.S: RV64 bitwise merge
- rv64up/slx.S: RV64 funnel shift left
- rv64up/srx.S: RV64 funnel shift right

Updated Makefrags to include new tests.
All tests verified passing with spike-cosim.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
The complete set of instructions added for RV32 are:
  PSSHL.HS SSHL PSSHL.DHS PSSHL.DWS
  PSSHLR.HS SSHLR PSSHLR.DHS PSSHLR.DWS
And for RV64:
  PSSHL.HS PSSHL.WS SHL PNCLIPP.B PNCLIPP.H PNCLIPP.W
  PSSHLR.HS PSSHLR.WS SHLR PNCLIPUP.B PNCLIPUP.H PNCLIPUP.W

reference:
  https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-020.pdf
  https://www.jhauser.us/RISCV/ext-P/RVP-baseInstrs-Sail-020.txt

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao

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Update: 2026/06/03

  1. add vxsat checking
  2. fix multiplication and shift testcases

@aswaterman
aswaterman merged commit 34e6b6d into riscv-software-src:master Jun 3, 2026
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2 participants