riscv: add misa write side - #414
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romancardenas
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Aug 18, 2026
| // `misa` is WARL: a hart may ignore the write entirely, and disabling an | ||
| // extension while its state is live is up to the caller. Reading the register | ||
| // back is the only way to learn what took effect. | ||
| write_csr_as!(Misa, 0x301); |
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Instead of this, would it be possible to use the read_write_csr! macro?
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Yes, works for my use case, thank you!
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