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riscv: add misa write side #414

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riscv: add misa write side #414

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1 change: 1 addition & 0 deletions riscv/CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

### Changed

- `misa` is now generated by `read_write_csr!` instead of `read_only_csr!`.
- `Pmpcsr`: now generated by the `csr!`. The public `bits` field is replaced by the private field plus `.bits()` / `.into()`; `read_csr_as!` constructs values via `from_bits` so child modules (`pmpcfg0`, …) keep compiling.

## v0.16.1 - 2026-05-29
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6 changes: 2 additions & 4 deletions riscv/src/register/misa.rs
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@@ -1,19 +1,17 @@
//! misa register

#[cfg(target_arch = "riscv32")]
read_only_csr! {
read_write_csr! {
/// `misa` register
Misa: 0x301,
mask: 0xc3ff_ffff,
sentinel: 0,
}

#[cfg(not(target_arch = "riscv32"))]
read_only_csr! {
read_write_csr! {
/// `misa` register
Misa: 0x301,
mask: 0xc000_0000_03ff_ffff,
sentinel: 0,
}

csr_field_enum! {
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