IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
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May 9, 2025 - Python
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microelectronics
Here are 46 public repositories matching this topic...
Rsyn – An Extensible Physical Synthesis Framework
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Jul 20, 2024 - C++
Simulating and emulating semiconductor fabrication processes
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May 16, 2025 - C++
A repository for embedded systems learning portals
arduino gpio i2c electronics gnu-linux adafruit gcc embedded-systems spi pi4j rs232 avr-programming pwm embedded-linux microelectronics dynamic-memory-allocation c-programming-language engineering-books embedded-engineering dynamic-memory-management
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Oct 29, 2022 - Markdown
Simple UVM phase jumping
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Feb 6, 2020 - SystemVerilog
A tool for matching devices in analog layout
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Feb 11, 2023 - Python
A personal collection of documents usually describing cutting-edge technology and research
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Jul 10, 2017
This is a tutorial to do analog design with open-source resources. It includes installation process, design procedure, layout...
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Jan 25, 2025
Simulating ADC background calibration algorithms in OpenCL
python simulation electronics opencl calibration adc heterogeneous-parallel-programming ica microelectronics analog-to-digital-converter
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Oct 25, 2023 - Python
Julia port of Prof. Boris Murmann's gm/ID Starter Kit https://web.stanford.edu/~murmann/gmid
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Dec 29, 2022 - Julia
Repository for open-source tools to VLSI design
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Jul 18, 2024 - Shell
Project made in Introduction to Microelectronics class
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Nov 20, 2023 - C
DLX processor implementation and improvement
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Jul 18, 2017 - Verilog
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
design fpga communication-protocol digital hardware electronics processor master-slave verilog vivado floating-point intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis arty-s7
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Apr 13, 2024 - VHDL
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
design pipeline digital hardware electronics processor vivado systemverilog risc 16-bit integrated-circuits microelectronics
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Apr 23, 2024 - SystemVerilog
A Personal blog describing various technical and research works.
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Jun 21, 2018 - CSS
Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)
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Jun 12, 2024 - Verilog
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
design communication-protocol pipeline digital hardware electronics signal-processing processor master-slave verilog fft vivado intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis
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Apr 13, 2024 - VHDL
Repositório com todos os passos necessários para instalar e usar o software Cadence .
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Apr 24, 2025 - Shell
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