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[WIP] System Verilog Testing #3 #3114

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@loglav03 loglav03 commented Jun 5, 2025

Description

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

AlexandreSinger and others added 22 commits February 7, 2025 17:44
The system verilog regression tests were put into the currently
not-working nightly tests. Since they are so small, putting them in the
GitHub runners tests instead so they do not regress.

The strong parmys test also has system verilog tests (I think); however,
that test may be too large for the GitHub runners. We may consider
moving that test to the SAVI workflows in the future.
Change install path
paths corrected
check synlig path
update CPU core
Run the default cmake --build
reduce build proc
Synlig Hardcoded Paths resolved
update synlig path
edited to relaunch the test
change CMAKE_BINARY_DIR to CMAKE_CURRENT_SOURCE_DIR. CI use separate build directions.
add debug message
limited cpu core
@github-actions github-actions bot added infra Project Infrastructure lang-python Python code lang-make CMake/Make code external_libs labels Jun 5, 2025
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