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stm32h7rs run application in external flash memory XIP #88052

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e0a0ced
soc: st: stm32 Kconfig to retrieve the external Flash Base address
FRASTM May 5, 2025
b8c3fc5
drivers: flash: stm32 xspi driver supports clock domain config
FRASTM May 27, 2024
2cd7b4e
drivers: flash: stm32 xspi drivers supporting the stm32h7r/s mcu
FRASTM May 31, 2024
fbf4218
drivers: clock control: stm32H7RS has a PLL2 & 3 or HCLK5 output
FRASTM Apr 3, 2025
7aa74d8
dts: arm: stm32h7rs mcu with xspi instance
FRASTM May 30, 2024
6809cf6
boards: st: stm32h7s3l8 nucleo board supporting xspi instance
FRASTM Nov 18, 2024
72b3a92
boards: arm: stm32h7s78 disco kit supporting xspi instance
FRASTM May 27, 2024
f4799af
boards: st: stm32h7s3l8 nucleo board for XiP on external flash
FRASTM Nov 18, 2024
120412f
boards: arm: stm32h7s78 disco kit for XiP on external flash
FRASTM May 27, 2024
318e63c
samples: appli dev: code reloc running on stm32h7rs target boards
FRASTM May 5, 2025
f8230cc
samples: sysbuild: with mcu_boot on the stm32h7rs targets
FRASTM May 7, 2025
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5 changes: 5 additions & 0 deletions boards/st/nucleo_h7s3l8/board.cmake
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Original file line number Diff line number Diff line change
@@ -1,7 +1,12 @@
# SPDX-License-Identifier: Apache-2.0

# keep first
if(CONFIG_STM32_MEMMAP OR (CONFIG_XIP AND CONFIG_BOOTLOADER_MCUBOOT))
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(stm32cubeprogrammer "--extload=MX25UW25645G_NUCLEO-H7S3L8.stldr")
else()
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw" )
endif()

board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)

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82 changes: 82 additions & 0 deletions boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts
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Expand Up @@ -53,6 +53,15 @@
led2 = &red_led;
sw0 = &user_button;
watchdog0 = &iwdg;
spi-flash0 = &mx25uw25645;
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I cannot seem to find where this alias is used in-tree.

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in the https://github.com/mcu-tools/mcuboot/blob/main/boot/zephyr/flash_map_extended.c, the FLASH_DEVICE_ID is defined as SPI_FLASH_0_ID

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Ah, then it should probably be documented @nordicjm

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it is not, it is like that for specific platforms that the owners have added

};

ext_memory: memory@70000000 {
compatible = "zephyr,memory-region";
reg = <0x70000000 DT_SIZE_M(64)>;
zephyr,memory-region = "EXTMEM";
/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
};
};

Expand Down Expand Up @@ -85,6 +94,19 @@
status = "okay";
};

/* PLL2 for clocking the xspi peripheral */
&pll2 {
div-m = <12>;
mul-n = <200>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
div-s = <2>;
div-t = <2>;
clocks = <&clk_hse>;
status = "okay";
};

&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(200)>;
Expand Down Expand Up @@ -139,3 +161,63 @@
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};

&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

/* Set the partitions with first MB to make use of the whole Bank1 */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
};
};

&xspi2 {
pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1
&xspim_p2_io0_pn2 &xspim_p2_io1_pn3
&xspim_p2_io2_pn4 &xspim_p2_io3_pn5
&xspim_p2_io4_pn8 &xspim_p2_io5_pn9
&xspim_p2_io6_pn10 &xspim_p2_io7_pn11
&xspim_p2_dqs0_pn0>;
pinctrl-names = "default";

status = "okay";

mx25uw25645: xspi-nor-flash@0 {
compatible = "st,stm32-xspi-nor";
reg = <0>;
size = <DT_SIZE_M(256)>; /* 256Mbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
spi-bus-width = <XSPI_OCTO_MODE>;
data-rate = <XSPI_DTR_TRANSFER>;
four-byte-opcodes;
status = "okay";

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

slot0_partition: partition@0 {
label = "image-0";
reg = <0x00000000 DT_SIZE_K(512)>;
};
slot1_partition: partition@80000 {
label = "image-1";
reg = <0x0080000 DT_SIZE_K(512)>;
};
scratch_partition: partition@100000 {
label = "image-scratch";
reg = <0x00100000 DT_SIZE_K(64)>;
};
storage_partition: partition@110000 {
label = "storage";
reg = <0x00110000 DT_SIZE_K(64)>;
};
};
};
};
1 change: 1 addition & 0 deletions boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml
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Expand Up @@ -12,4 +12,5 @@ supported:
- watchdog
- entropy
- adc
- octospi
vendor: st
6 changes: 6 additions & 0 deletions boards/st/stm32h7s78_dk/board.cmake
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Original file line number Diff line number Diff line change
@@ -1,7 +1,13 @@
# SPDX-License-Identifier: Apache-2.0

# keep first
if(CONFIG_STM32_MEMMAP OR (CONFIG_XIP AND CONFIG_BOOTLOADER_MCUBOOT))
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(stm32cubeprogrammer "--extload=MX66UW1G45G_STM32H7S78-DK.stldr")
else()
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw" )
endif()

board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)

# keep first
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69 changes: 69 additions & 0 deletions boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
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Expand Up @@ -57,6 +57,15 @@
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
spi-flash0 = &mx66uw1g45;
};

ext_memory: memory@70000000 {
compatible = "zephyr,memory-region";
reg = <0x70000000 DT_SIZE_M(64)>;
zephyr,memory-region = "EXTMEM";
/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
};
};

Expand Down Expand Up @@ -173,6 +182,66 @@
pinctrl-names = "default";
};

&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

/* Set the partitions with first MB to make use of the whole Bank1 */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
};
};

&xspi2 {
pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1
&xspim_p2_io0_pn2 &xspim_p2_io1_pn3
&xspim_p2_io2_pn4 &xspim_p2_io3_pn5
&xspim_p2_io4_pn8 &xspim_p2_io5_pn9
&xspim_p2_io6_pn10 &xspim_p2_io7_pn11
&xspim_p2_dqs0_pn0>;
pinctrl-names = "default";

status = "okay";

mx66uw1g45: xspi-nor-flash@0 {
compatible = "st,stm32-xspi-nor";
reg = <0>;
size = <DT_SIZE_M(1024)>; /* 1 Gbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
spi-bus-width = <XSPI_OCTO_MODE>;
data-rate = <XSPI_DTR_TRANSFER>;
four-byte-opcodes;
status = "okay";

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

slot0_partition: partition@0 {
label = "image-0";
reg = <0x00000000 DT_SIZE_K(512)>;
};
slot1_partition: partition@80000 {
label = "image-1";
reg = <0x0080000 DT_SIZE_K(512)>;
};
scratch_partition: partition@100000 {
label = "image-scratch";
reg = <0x00100000 DT_SIZE_K(64)>;
};
storage_partition: partition@110000 {
label = "storage";
reg = <0x00110000 DT_SIZE_K(64)>;
};
};
};
};

&die_temp {
status = "okay";
};
Expand Down
2 changes: 1 addition & 1 deletion boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,6 @@ supported:
- watchdog
- entropy
- adc
- usb_device
- usbd
- octospi
vendor: st
12 changes: 11 additions & 1 deletion drivers/clock_control/clock_stm32_ll_h7.c
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Expand Up @@ -337,6 +337,12 @@ int enabled_clock(uint32_t src_clk)
((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
(src_clk == STM32_SRC_HCLK5) ||
((src_clk == STM32_SRC_PLL2_S) && IS_ENABLED(STM32_PLL2_S_ENABLED)) ||
((src_clk == STM32_SRC_PLL2_T) && IS_ENABLED(STM32_PLL2_T_ENABLED)) ||
((src_clk == STM32_SRC_PLL3_S) && IS_ENABLED(STM32_PLL3_S_ENABLED)) ||
#endif
((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {
return 0;
}
Expand Down Expand Up @@ -460,6 +466,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
case STM32_CLOCK_BUS_AHB2:
case STM32_CLOCK_BUS_AHB3:
case STM32_CLOCK_BUS_AHB4:
#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
/* HCLK5 i a possible source clock for some peripherals */
case STM32_SRC_HCLK5:
#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
*rate = ahb_clock;
break;
case STM32_CLOCK_BUS_APB1:
Expand Down Expand Up @@ -544,7 +554,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
STM32_PLL_N_MULTIPLIER,
STM32_PLL_S_DIVISOR);
break;
/* PLL 1 has no T-divider */
/* PLL 1 has no T-divider */
#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
#endif /* STM32_PLL_ENABLED */
#if defined(STM32_PLL2_ENABLED)
Expand Down
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