Taskfile workflow overhaul + chip-level LVS + configurable top-cell name

[dnltz]

Reworks the Taskfile-based flows into clear asic: / sim: namespaces, adds a
chip-level LVS flow, makes the design top-cell name configurable via a single
TOPCELL variable, and adds guard rails (preconditions) so common mistakes fail
with a helpful message instead of a cryptic tool error. Also auto-forwards
SpinalHDL blackbox Verilog to OpenROAD, and bumps Nafarr/Zibal to pull in the

Changes

Task reorganization (Taskfile: Rework tasks)

• Move ASIC and simulation tasks into dedicated asic: and sim: namespaces
  (alongside the existing fpga:/flash:/zephyr: includes).
• Rename tasks to better match intent: layout→build, filler→fill,
  run-drc→drc, view-simulation→waves (old names kept as aliases).
• Collapse near-duplicate tasks into one parameterized task:
  • open-*/view-* KLayout & OpenROAD → asic:klayout / asic:openroad
    with mode=empty|drc.
  • cosim/cosim-gui and emulate/emulate-gui → single task with gui=1.

Chip-level LVS (Taskfile: asic: Add LVS task)

• asic:netlist generates the CDL schematic netlist via ORFS.
• asic:lvs generates the netlist and runs the KLayout LVS deck against the
  final GDS. (Library tasks lib-generate-netlist / lib-run-lvs land in Zibal.)

Configurable top-cell name (Taskfile: Add configurable chip top-cell name via TOPCELL)

• New TOPCELL variable (default <TARGET>Top) threaded through the container
  env into both ORFS and the SpinalHDL generators, renaming the whole design
  top cell from one place: Verilog module, DESIGN_NAME/DESIGN_NICKNAME,
  results dir, --topcell, and generated file names.
• Applied in the ElemRV-H and ElemRV-C generators via setDefinitionName +
  setTopCellName. Default-preserving: unset TOPCELL reproduces current behavior.

Preconditions

• asic:build fails with a clear "Design not prepared — run asic:prepare" message
  when the SoC metadata (<top>.mk) is missing.
• sim:emulate / sim:cosim fail with a "build firmware first" message when the
  image_container.img is missing.

Blackbox Verilog (hardware: elemrv_{h,c}: Automatically add blackbox Verilog)

• Forward the blackbox Verilog files SpinalHDL reports to OpenROADTools so they
  are added to the OpenROAD flow automatically.

Docs / CI

• Sweep README, docs/source/**, and .travis.yml to the new task names.

Manifest

• Bump Nafarr and Zibal to the revisions carrying the LVS library tasks and the
  OpenROADTools top-cell / blackbox changes.

Notes / testing

• Task namespacing, renames, TOPCELL propagation, and preconditions were
  verified via task --dry (default vs. override paths, precondition firing).
• The SpinalHDL generator changes (setDefinitionName/setTopCellName) have not
  been compiled here — confirm with a task asic:prepare (and that synthesis'
  -top $DESIGN_NAME matches the emitted module).
• LVS has not been run end-to-end; the netlist-generation path depends on the
  ORFS/OpenROAD version providing a CDL for the target PDK.