Taskfile workflow overhaul + chip-level LVS + configurable top-cell name - #28

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dnltz merged 7 commits into

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WIP/dnltz/lvs-and-topcell

Jul 22, 2026

Commits on Jul 21, 2026

hardware: elemrv_{h,c}: Automatically add blackbox Verilog
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9dd3c7d
Taskfile: Rework tasks
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Taskfile: asic: Add precondition for build
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e680ebb
Taskfile: asic: Add LVS task
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e83fe74
Taskfile: Add configurable chip top-cell name via TOPCELL
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921e82b
Taskfile: sim: Add precondition
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Manifest: Bump Nafarr and Zibal
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