Taskfile workflow overhaul + chip-level LVS + configurable top-cell name - #28
Merged
Travis CI / Travis CI - Pull Request
succeeded
Jul 21, 2026 in 44m 0s
Build Passed
Details
This is a pull request build.
It is running a build against the merge commit, after merging #28 Taskfile workflow overhaul + chip-level LVS + configurable top-cell name.
Any changes that have been made to the main branch before the build ran are also included.
Jobs and Stages
This build only has a single job.
You can use jobs to test against multiple versions of your runtime or dependencies, or to speed up your build.
Build Configuration
| Build Option | Setting |
|---|---|
| Language | Generic |
| Operating System | Linux (Noble) |
Build Configuration
{
"timeout": 10800,
"language": "generic",
"os": [
"linux"
],
"dist": "noble",
"branches": {
"only": [
"main"
]
},
"if": "type IN (pull_request, cron)",
"cache": {
"directories": [
"$HOME/.podman-cache"
]
},
"install": [
"sudo apt-get update",
"sudo apt-get install -y podman uidmap slirp4netns",
"git config --global color.ui false",
"sudo snap install task --classic",
"sudo apt-get update",
"sudo apt-get install -y virtualenv"
],
"script": [
"if [ \"$TRAVIS_EVENT_TYPE\" = \"cron\" ]; then\n BRANCH=\"main\"\n MANIFEST_SUFFIX=\"manifest_suffix=-nightly\"\nelse\n BRANCH=\"${TRAVIS_PULL_REQUEST_BRANCH:-main}\"\n MANIFEST_SUFFIX=\"\"\nfi\n",
"CI=true IS_HEADLESS=true task install branch=${BRANCH} ${MANIFEST_SUFFIX}",
"CI=true IS_HEADLESS=true task install-zephyr",
"CI=true IS_HEADLESS=true task SOC=ElemRV-H TARGET=SG13CMOS5L asic:prepare",
"CI=true IS_HEADLESS=true task SOC=ElemRV-C TARGET=SG13CMOS5L asic:prepare",
"CI=true IS_HEADLESS=true task SOC=ElemRV-N TARGET=SG13G2 asic:prepare",
"CI=true IS_HEADLESS=true task SOC=ElemRV-H baremetal:compile",
"CI=true IS_HEADLESS=true task SOC=ElemRV-C baremetal:compile",
"CI=true IS_HEADLESS=true task SOC=ElemRV-N baremetal:compile",
"CI=true IS_HEADLESS=true task SOC=ElemRV-H TARGET=SG13CMOS5L fpga:prepare",
"CI=true IS_HEADLESS=true task SOC=ElemRV-C TARGET=SG13CMOS5L fpga:prepare",
"CI=true IS_HEADLESS=true task SOC=ElemRV-N TARGET=SG13G2 fpga:prepare",
"CI=true IS_HEADLESS=true task SOC=ElemRV-H zephyr:compile",
"CI=true IS_HEADLESS=true task SOC=ElemRV-N zephyr:compile",
"CI=true IS_HEADLESS=true task SOC=ElemRV-H TARGET=SG13CMOS5L fpga:synthesize",
"CI=true IS_HEADLESS=true task SOC=ElemRV-C TARGET=SG13CMOS5L fpga:synthesize",
"CI=true IS_HEADLESS=true task SOC=ElemRV-N TARGET=SG13G2 fpga:synthesize"
],
"notifications": {
"email": [
{
"on_success": "never",
"on_failure": "always",
"recipients": [
"nightly.reports@aesc-silicon.de"
]
}
]
}
}
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