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Shehrozkashif
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@Shehrozkashif Shehrozkashif commented Mar 28, 2025

This PR adds the Zclsd extension to the database. Zclsd introduces compressed load/store pair instructions for RV32 by reusing RV64-only instruction encodings, which helps improve code density and performance when leveraging a wider than XLEN memory interface. It defines 16-bit instruction encodings and utilizes the same even-odd register pairing as the Zdinx extension. Additionally, Zclsd depends on the Zilsd and Zca extensions, and it is incompatible with Zcf due to overlapping encodings
Closes #572

@Shehrozkashif Shehrozkashif force-pushed the Zclsd_extension branch 2 times, most recently from 02d3cc1 to fb4e75d Compare April 7, 2025 19:40
@Shehrozkashif Shehrozkashif requested a review from AFOliveira April 7, 2025 20:32
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Comments apply to all the instructions.

@ThinkOpenly
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@Shehrozkashif, did you see that there are "conflicts that must be resolved"?

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When this content has all been merged into arch/inst/C/c.sd.yaml, this file should be removed.

@Shehrozkashif
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@ThinkOpenly yes I can see the conflict Should I keep the new logic, the main branch version, or try to merge both?

@AFOliveira
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@ThinkOpenly yes I can see the conflict Should I keep the new logic, the main branch version, or try to merge both?

I know your comment is intended to Paul, but I would say to try to manually merge and see what has been done.

If it is the work you have been doing, probably just review the upstream changes, and if you agree, keep them, if you dont agree just push changes to them

@Shehrozkashif
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Thanks for the advice, @AFOliveira! I'll go ahead and manually merge the changes and review the differences. If the upstream changes align with my work, I’ll keep them; if not, I’ll make the necessary adjustments. Appreciate the help!

@AFOliveira
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Thanks for the advice, @AFOliveira! I'll go ahead and manually merge the changes and review the differences. If the upstream changes align with my work, I’ll keep them; if not, I’ll make the necessary adjustments. Appreciate the help!

If in doubt, use git blame to understand who did the changes and try reaching out to them, or even ask for the review after you merge

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@Shehrozkashif Can you please resolve conversations that are marked as outdated? Github won't let you merge whilst they aren't marked as resolved and when opening a PR it makes it cluttered

@ayosher
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ayosher commented May 5, 2025

Folks,
What is the plan? When this extension is planned to proceed?

@Shehrozkashif
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@ayosher Apologies for the delay I’ll try to complete it as soon as possible.

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generally, let's move all the register names to x* (xd, xs1, xs2).

definedBy:
anyOf:
- C
- Zca
base: 64
- Zclsd
assembly: xd, imm(xs1)
encoding:
match: 011-----------00
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We need separate encodings for RV32/RV64 since in RV32 xd cannot be odd.

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do I have to put them in seprate files ?

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See arch/inst/I/slli.yaml for an example of how to specify multiple encodings in one file.

@@ -13,6 +13,7 @@ definedBy:
anyOf:
- C
- Zca
- Zclsd
base: 64
assembly: xs2, imm(xs1)
encoding:
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separate RV32/RV64

rd, offset(sp). C.LDSP is only valid when rd≠x0; the code points with rd=x0 are reserved.
definedBy: Zclsd
assembly: rd, offset(sp)
encoding:
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separate encoding. RV32 xd == 0 or odd is reserved

offset(rs1').
definedBy: Zclsd
assembly: c.sd rs2, offset(rs1)
encoding:
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separate encoding

`sd rs2, offset(sp)`.
definedBy: Zclsd
assembly: rs2, offset(sp)
encoding:
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separate encoding

# SPDX-License-Identifier: BSD-2-Clause
if (xlen() == 32) {
if (implemented?(ExtensionName::Zclsd)) {
Bits<128> val = read_memory<128>(X[creg2reg(xs1)] + imm, $encoding);
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The "128" here should be "64". We're loading a register pair. In RV32 mode, each register is 32 bits, so a pair would be 64 bits.

Comment on lines 53 to 54
X[creg2reg(xd)] = val[63:0];
X[creg2reg(xd + 1)] = val[127:64];
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And these ranges should, respectively, be: 31:0 and 63:32.

_ => report_invalid_width(__FILE__, __LINE__, width, "load")
}
}
}
}

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This needs to be retained, at the end of the Sail code.

Comment on lines +18 to +19
- name: xd
location: 11-7
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add a "not" statement here, also including "0" as an invalid value.

Oh, wait. This instruction also exists at arch/inst/c.ldsp.yaml. You need to do the same sort of merging with this instruction into that file as you did from c.ld.yaml. Does that make sense?

This is also true for c.sdsp.

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yes ill add it in both

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remove this file

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can you please explain the reason of removing it ?

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Because you're now defining the RV32 version of this instruction in arch/inst/C/c.sd.yaml, so this file is redundant.

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Understood

definedBy:
anyOf:
- C
- Zca
- Zclsd
base: 64
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remove this line, since it can be defined for RV32 with your changes.

Comment on lines 41 to 47
if (xd == 0) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}

if (xlen() == 32 && (creg2reg(xd) % 2 != 0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
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with the "not" statement in place, you don't need either of these two checks.

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The RV32 changes here need to be merged into arch/inst/c.sdsp.yaml, then this file removed.

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Add Zclsd Extension Data
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